On DRV8378-Q1 SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out diagnostic information. DRV8378-Q1 uses SPI mode 0 (Data is sampled on the rising edge and shifted out on the falling edge). Refer to timing diagram Figure 6-1. The SPI operates in secondary mode and connects to a controller. The SPI input data (SDI) word consists of a 24-bit word, with one read or write bit, a parity bit, 6-bit address and 15 bits of data with a parity bit. The SPI output consists of 24 bit word, with a 8 bits of status information (STS register) and 16-bit register data.

A valid frame must meet the following conditions:

• The SCLK pin must be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin must be pulled high for at least 400 ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed in the Hi-Z state.
• Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK pin.
• The most significant bit (MSB) is shifted in and out first.
• A full 24 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 24 bits, a frame error occurs and the data word is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following the 8-bit status data.

The SPI registers are reset to the default settings on power up and in sleep mode