SLVSNG2 August   2026 DRV8378-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings AUTO
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Mode Timings
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Feature Description
      1. 7.3.1 Output Stage
      2. 7.3.2 Device Interface Modes
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware Interface
      3. 7.3.3 Control Modes
        1. 7.3.3.1 3x PWM Mode (PWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD with RMODE or to GVDD)
        2. 7.3.3.2 6x PWM Mode (PWM_MODE = 00b or 01b or MODE_SR Pin Tied to AGND or in Hi-Z)
        3. 7.3.3.3 DRV8378G Control mode with External GVDD
      4. 7.3.4 GVDD Linear Voltage Regulator
      5. 7.3.5 Charge Pump
    4. 7.4  Slew Rate Control
    5. 7.5  Cross Conduction (Dead Time)
    6. 7.6  Propagation Delay
    7. 7.7  Pin Diagrams
      1. 7.7.1 Logic Level Input Pin (Internal Pulldown)
      2. 7.7.2 Logic Level Input Pin (Internal Pullup)
      3. 7.7.3 Open Drain Pin
      4. 7.7.4 Push Pull Pin
    8. 7.8  Current Sense Amplifiers
      1. 7.8.1 Current Sense Amplifier Operation (29-pin variant)
    9. 7.9  Active Demagnetization
      1. 7.9.1 Automatic Synchronous Rectification Mode (ASR Mode)
        1. 7.9.1.1 Automatic Synchronous Rectification in Commutation
        2. 7.9.1.2 Automatic Synchronous Rectification in PWM Mode
      2. 7.9.2 Automatic Asynchronous Rectification Mode (AAR Mode)
    10. 7.10 Cycle-by-Cycle Current Limit
      1. 7.10.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
    11. 7.11 Protections
      1. 7.11.1 Overcurrent Protection (OCP)
        1. 7.11.1.1 OCP Latched Shutdown (OCP_MODE = 00b)
        2. 7.11.1.2 OCP Automatic Retry (OCP_MODE = 01b)
        3. 7.11.1.3 OCP Disabled (OCP_MODE = 11b)
        4. 7.11.1.4 OCP Report Only (OCP_MODE = 10b)
      2. 7.11.2 VM Supply Undervoltage Lockout (RESET)
      3. 7.11.3 GVDD Undervoltage Lockout (GVDD_UV)
      4. 7.11.4 VCP Charge Pump Undervoltage Lockout (CPUV)
      5. 7.11.5 Over Voltage Protections (OV)
      6. 7.11.6 Thermal Warning (OTW)
      7. 7.11.7 Thermal Shutdown (OTS)
    12. 7.12 Device Functional Modes
      1. 7.12.1 Functional Modes
        1. 7.12.1.1 Sleep Mode
        2. 7.12.1.2 Operating Mode
        3. 7.12.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 7.12.2 DRVOFF functionality
    13. 7.13 SPI Communication
      1. 7.13.1 Programming
        1. 7.13.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 CONTROL Registers
    2. 8.2 STATUS Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Power Supply Recommendations
      1. 9.2.1 Bulk Capacitance
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
      3. 9.3.3 Thermal Considerations
        1. 9.3.3.1 Power Dissipation
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information

5 Pin Configuration and Functions

DRV8378-Q1 DRV8378-Q1 29-Pin VQFN Top ViewFigure 5-1 DRV8378-Q1 29-Pin VQFN Top View
Table 5-1 Pin Functions
PIN 29-pin VQFN Package TYPE(1) DESCRIPTION
NAME DRV8378H DRV8378S DRV8378G
AGND 28 28 28 GND Device analog ground. Refer layout for connections recommendation.
CP 29 29 29 PWR O Charge pump output. Connect a X5R or X7R, 1µF, 16V ceramic capacitor between the CP and VM pins.
CPH 1 1 1 PWR O Charge pump switching node. Connect a X5R or X7R, 100nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
CPL 2 2 2 PWR O
DRVOFF 21 21 21 I When this pin is pulled high the six MOSFETs in the power stage are turned OFF making all outputs Hi-Z.
GAIN 17 — — I Current Sense Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
ILIMIT 26 — — I Sets the threshold for phase current used in cycle by cycle current
INHA 12 12 12 I High-side driver control input for OUTA. This pin controls the output of the high-side MOSFET.
INHB 13 13 13 I High-side driver control input for OUTB. This pin controls the output of the high-side MOSFET.
INHC 14 14 14 I High-side driver control input for OUTC. This pin controls the output of the high-side MOSFET.
INLA 9 9 9 I Low-side driver control input for OUTA. This pin controls the output of the low-side MOSFET.
INLB 10 10 10 I Low-side driver control input for OUTB. This pin controls the output of the low-side MOSFET.
INLC 11 11 11 I Low-side driver control input for OUTC. This pin controls the output of the low-side MOSFET.
MODE_SR 16 — — I PWM input mode setting. This pin is a 4-level input pin set by an external resistor.
nFAULT 8 8 8 O Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 2.2V to 5.0V. If external supply is used to pull up nFAULT, make sure nFAULT is pulled to >2.2V on power up or the device can enter test mode
nSCS — 23 23 I Serial chip select. A logic low on this pin enables serial interface communication.
nSLEEP 18 18 18 I Driver nSLEEP. When this pin is logic low, the device goes into a low-power sleep mode. An 20 to 40µs low pulse can be used to reset fault conditions without entering sleep mode.
OUTA 7 7 7 PWR O Half bridge output A
OUTB 5 5 5 PWR O Half bridge output B
OUTC 3 3 3 PWR O Half bridge output C
PGND 19, 20 19, 20 19, 20 GND Device power ground. Refer layout for connections recommendation.
SCLK — 15 15 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin (SPI devices).
SDI — 17 17 I Serial data input. Data is captured on the falling edge of the SCLK pin (SPI devices).
SDO — 16 16 O Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor (SPI devices).
SLEW 15 — — I Slew rate control setting. This pin is a 4-level input pin set by an external resistor.
SOA 24 24 24 O Current sense amplifier output. For 29-pin variant of DRV8378H/S:The current sense amplifier output is a voltage proportional to the low side FET current. Supports capacitive load or low pass filter (resistor in series and capacitor to AGND). For 23-pin variant of DRV8378H: The current sense amplifier output is a current proportional to the low side FET current. Need an external resistor from SOA to AGND to convert current to voltage.
SOB 25 25 25 O Current sense amplifier output. For 29-pin variant of DRV8378H/S:The current sense amplifier output is a voltage proportional to the low side FET current. Supports capacitive load or low pass filter (resistor in series and capacitor to GND). For 23-pin variant of DRV8378H: The current sense amplifier output is a current proportional to the low side FET current. Need an external resistor from SOB to GND to convert current to voltage.
SOC 26 26 26 O Current sense amplifier output. For 29-pin variant of DRV8378H/S:The current sense amplifier output is a voltage proportional to the low side FET current. Supports capacitive load or low pass filter (resistor in series and capacitor to AGND). For 23-pin variant of DRV8378H: The current sense amplifier output is a current proportional to the low side FET current. Need an external resistor from SOC to AGND to convert current to voltage.
VM 4, 6 4, 6 4, 6 PWR I Power supply. Connect to motor supply voltage; bypass to PGND with two 0.1µF capacitors (for each pin) plus one bulk capacitor rated for VM. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
VREF 27 27 27 PWR/I

Current sense amplifier reference. Connect a X5R or X7R, 0.1μF, 6.3V ceramic capacitor between the VREF and AGND pins.
GVDD 22 22 22 PWR I/O For DRV8378H/S: 5V internal regulator output. Connect an X5R or X7R, 1μF, 10V ceramic capacitor between the GVDD and AGND pins. This regulator can source up to 30mA externally.

For DRV8378G: External power supply input for the internal predriver. Connect an X5R or X7R, 1μF, 10V ceramic capacitor between the GVDD and AGND pins.
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect