SLVT251 July   2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 High-Voltage Stackable Architecture
      2. 2.2.2 Electrochemical Impedance Spectroscopy (EIS) Subsystem
      3. 2.2.3 EIS Synchronization Requirement
      4. 2.2.4 PWM Input as Crystal of the First BQ79826Z-Q1
      5. 2.2.5 Temperature Sensing and Multiplexer Network
      6. 2.2.6 Cell Balancing Circuit and Operation
      7. 2.2.7 MCU and System Control Architecture
      8. 2.2.8 Protection and On-Board Diagnostics
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ79826Z-Q1
      2. 2.3.2 TMUX1308
      3. 2.3.3 TMP61
      4. 2.3.4 SN74LXC1T14
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software
    3. 3.3 Test Setup
    4. 3.4 Pack Test Results
      1. 3.4.1 Cell Voltage Reliability Test
      2. 3.4.2 EIS Measurement Repeatability
      3. 3.4.3 Pack EIS Measurement Nyquist Plot
      4. 3.4.4 Current Consumption per BQ79826Z-Q1
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
    2. 4.2 Tools and Software
      1. 4.2.1 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5.     Trademarks
  11. 5About the Author

3.2 Software

Software framework is one of the most critical design considerations for TIDA-010978, adopting complete layered modular architecture with clear division of labor and strong scalability. The whole software is divided into hardware driver layer, middleware layer, application layer, and upper computer GUI layer.

Hardware diver layer: includes SPI, CAN, ePWM, eCAP, ADC, GPIO, multiplexer and other peripheral drivers, providing standard calling interfaces for upper layers.

Middleware layer: integrates temperature conversion, voltage filtering, communication protocol parsing, EIS raw data preprocessing and balancing logic algorithm.

Application layer: Adopts multi-cycle real-time task scheduling:

  • 20μs high-priority task: EIS closed-loop control, PWM timing and ADC synchronous sampling
  • 100ms task: Cell voltage and temperature data refresh, normal status upload
  • 5s task: AFE status detection and fault diagnosis update
  • 300s task: Full-band EIS scanning and spectrum data storage

Upper Computer GUI Interaction Layer: Implements data parsing, protocol interaction, real-time curve display, parameter configuration and automated test interface.

Task priority is strictly divided to maintain that protection and EIS synchronous control are not blocked by low-priority tasks. Fault handling, low-power switching and EIS flow logic are embedded in each layer to maintain system stability and functional integrity.