SLVUCJ9 February   2023 LP8764-Q1 , TPS6594-Q1

 

  1.   PDN-0A User's Guide for Powering J7AEP with the TPS6594-Q1 and LP8764-Q1 PMICs
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Exiting LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

5.4 LDO Settings

These settings detail the voltages, configurations, and monitoring of the LDO rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in GUID-C4EB5B6E-C9E2-46E0-B5A5-085D4EE72490.html#GUID-C4EB5B6E-C9E2-46E0-B5A5-085D4EE72490.

After the GUID-9E18C445-7F77-47F6-9860-9BB40CA11E88.html#GUID-9E18C445-7F77-47F6-9860-9BB40CA11E88 sequence has completed, the LDOx_EN and LDOx_VMON_EN bits are set and the LDOx_RV_SEL bit is cleared for all LDOs. The other bits remain unchanged, but are still accessible via I2C.

Table 5-4 LDO NVM Settings
Register NameField NameTPS65941120-Q1TPS65941421-Q1
ValueDescriptionValueDescription
LDO1_CTRLLDO1_EN0x0Disabled; LDO1 regulator.0x0Disabled; LDO1 regulator.
LDO1_SLOW_RAMP0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO1_PLDN0x1125 Ohm0x1125 Ohm
LDO1_VMON_EN0x0Disable OV and UV comparators.0x0Disable OV and UV comparators.
LDO1_RV_SEL0x1Enabled0x1Enabled
LDO2_CTRLLDO2_EN0x0Disabled; LDO2 regulator.0x0Disabled; LDO2 regulator.
LDO2_SLOW_RAMP0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO2_PLDN0x1125 Ohm0x1125 Ohm
LDO2_VMON_EN0x0Disabled; OV and UV comparators.0x0Disabled; OV and UV comparators.
LDO2_RV_SEL0x1Enabled0x1Enabled
LDO3_CTRLLDO3_EN0x0Disabled; LDO3 regulator.0x0Disabled; LDO3 regulator.
LDO3_SLOW_RAMP0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO3_PLDN0x1125 Ohm0x1125 Ohm
LDO3_VMON_EN0x0Disabled; OV and UV comparators.0x0Disabled; OV and UV comparators.
LDO3_RV_SEL0x1Enabled0x1Enabled
LDO4_CTRLLDO4_EN0x0Disabled; LDO4 regulator.0x0Disabled; LDO4 regulator.
LDO4_SLOW_RAMP0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET0x025mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO4_PLDN0x1125 Ohm0x1125 Ohm
LDO4_VMON_EN0x0Disabled; OV and UV comparators.0x0Disabled; OV and UV comparators.
LDO4_RV_SEL0x1Enabled0x1Enabled
LDO1_VOUTLDO1_VSET0x80.80 V0x80.80 V
LDO1_BYPASS0x0Linear regulator mode.0x0Linear regulator mode.
LDO2_VOUTLDO2_VSET0x3a3.30 V0x3a3.30 V
LDO2_BYPASS0x1Bypass mode.0x1Bypass mode.
LDO3_VOUTLDO3_VSET0x1c1.80 V0x80.80 V
LDO3_BYPASS0x0Linear regulator mode.0x0Linear regulator mode.
LDO4_VOUTLDO4_VSET0x381.800 V0x381.800 V
LDO1_PG_WINDOWLDO1_OV_THR0x3+5% / +50 mV0x3+5% / +50 mV
LDO1_UV_THR0x3-5% / -50 mV0x3-5% / -50 mV
LDO2_PG_WINDOWLDO2_OV_THR0x7+10% / +100mV0x7+10% / +100mV
LDO2_UV_THR0x7-10% / -100mV0x7-10% / -100mV
LDO3_PG_WINDOWLDO3_OV_THR0x3+5% / +50 mV0x3+5% / +50 mV
LDO3_UV_THR0x3-5% / -50 mV0x3-5% / -50 mV
LDO4_PG_WINDOWLDO4_OV_THR0x3+5% / +50 mV0x3+5% / +50 mV
LDO4_UV_THR0x3-5% / -50 mV0x3-5% / -50 mV