SLVUDB5A June   2025  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 General Configurations
      1. 2.1.1 Physical Access
      2. 2.1.2 Test Equipment and Setup
  8. 3Implementation Results
    1. 3.1 Test Setup and Procedures
      1. 3.1.1 Supply Ramped From 0V to 54V — Start-up
      2. 3.1.2 Power Up Into Short
      3. 3.1.3 Undervoltage Lockout
      4. 3.1.4 Overvoltage Lockout
      5. 3.1.5 Overcurrent Event
      6. 3.1.6 Output Hot Short
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Drawings
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6Revision History

4.2 PCB Drawings

Figure 4-3 and Figure 4-4 show the component placement of the EVM.

TPS1686-87EVM TPS1686-87EVM Board: Top AssemblyFigure 4-3 TPS1686-87EVM Board: Top Assembly
TPS1686-87EVM TPS1686-87EVM Board: Bottom AssemblyFigure 4-4 TPS1686-87EVM Board: Bottom Assembly
Note: Analog signal nets, such as IREF, IMON, and TEMP must be routed away as much as possible from power nets, such as VIN, VOUT, and PGND.