For enhanced control, the GUI also supports an “Advanced mode” that allows the user to more closely control how the ADC is configured. This mode can be enabled by checking the “Advanced Mode” checkbox after enabling the GUI updates to look like Figure 3-9. This allows access to the “JESD” control tab where the number of lanes can be edited. The number of channel, frame octets and samplers per frame variables are inferred based on other settings of the ADC. The user can also edit the encoding scheme used by the JESD link by default “8b10b” JESD204B is chosen, but the ADC also supports 64b66b JESD204C. This tab also calculates the exact SERDES rate of the JESD link as well as the required FPGA reference clock and SYSREF frequency, which are generated on the EVM from the provided external reference clock input.

If the operating mode is changed to “Enable DSP” on the ADC tab, then this allows access to the “DSP” tab of the ADC GUI. In this tab, the user can configure the ADC to average channels A+B, C+D or A+B+C+D. The Digital Down Converters (DDC) can also be configured on this page. Based on selections on this page, the JESD page updates the number of channels required to output the ADC’s data.

Once the user is satisfied with the configuration of the ADC, they can click program and then, if successful, can capture data and plot to HSDC Pro.

Figure 3-10 shows all the different dropdowns and entry available to the user in the DSP tab of the GUI.

Figure 3-11 shows all the different dropdowns and entry available to the user in the JESD tab of the GUI.