SLVUDB9 July   2025 ADC34RF72

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware and Software Setup
    1. 2.1  Board Overview
    2. 2.2  Required Equipment
    3. 2.3  Required Software Installation
    4. 2.4  Required TI Software to Install
    5. 2.5  3rd Party Software to Install
    6. 2.6  Software Environment Setup
    7. 2.7  Hardware Setup and Connections
    8. 2.8  ADC3xRF72 EVM Connections
    9. 2.9  TSW14J58 Data Capture Card Connections
    10. 2.10 Debug LEDs
    11. 2.11 EVM Jumpers and Switches
  9. 3ADC3xRF72 EVM Configuration and Programming
    1. 3.1  ADC EVM Quick Start
    2. 3.2  Power on all Boards and Signal Generators
    3. 3.3  Launch GSPS FPGA Server
    4. 3.4  Launch High-Speed Data Converter Professional (HSDC Pro) SW
    5. 3.5  Programming the ADC
    6. 3.6  Quick Start Mode
    7. 3.7  System Level Configuration Mode
    8. 3.8  Advanced Mode
    9. 3.9  Runtime Configuration
    10. 3.10 Exporting ADC3xRF72 Configuration and Python API usage
    11. 3.11 Further GUI Help
  10. 4Troubleshooting and FAQ
  11. 5Important Signal Routing
    1. 5.1 ADC Device Clock Routing
    2. 5.2 Board Modifications
      1. 5.2.1 ADC3xRF72 Analog Inputs
  12. 6Hardware Design Files
    1. 6.1 Schematics
    2. 6.2 PCB Layouts
    3. 6.3 Bill of Materials (BOM)
  13. 7Additional Information
    1. 7.1 Trademarks
  14. 8References

4 Troubleshooting and FAQ

Table 4-1 Troubleshooting and FAQ
Issue Troubleshooting Step
General Issues
  • Verify test setup shown in section Section 2 and repeat “ADC EVM quick start” section to verify basic functionality.
  • Check power supply to ADC EVM and TI Capture Card. If Power good LEDs on ADC EVM are not lit up then there is likely a power supply issue.
  • Check signal and clock connections
  • Make sure that the FMC connector is tightly secured
TI Capture Card cannot connect in GSPS FPGA Server Application
  • Make sure that all steps to setup 3rd party software are followed in section Section 2.6
  • Make sure that the diligent JTAG dongle is properly connected.
  • Using FT_Prog search for connected USB devices and make sure that the ‘Diligent USB Device’ is found correctly. If it initially is not found, disconnect dongle from board and replug in the micro USB cable then search.
  • If the issue still persists, launch a command prompt and type command ‘xsdb’ to launch the Xilinx debug server. If command prompt returns the error ‘xsdb’ is not recognized as an internal or external command operable program or batch file, then it is likely the environment variables have not been setup correctly.
  • If xsdb launches correctly type commands “connect” and then “targets” upon successful completion of these commands the command prompt shows xcku5p as one of the targets.
  • If connection of board in GSPS FPGA server is still unsuccessfu, uninstall and reinstall the application
ADC EVM cannot connect in GUI
  • Verify that the USB cable and daughter card are making solid connection.
  • Using FT_Prog verify that the ADC FTDI handle is found and matches the following “ADC3xRF72EVM_RevA”
ADC EVM fails programming
  • Make sure that device clock to ADC has enough power to the EVM (9dBm) and the frequency matches what is programmed in the GUI.
  • Make sure that all jumpers are in the default position. Particular care that jumper J24 is installed as this controls if the SPI programming signals for the ADC come from the PC via USB or from the FPGA via JTAG.
  • Check that the resetb signal is held low. Using the multimeter probe RSTb signal located on the GPIO header. This signal reads approximately 1.8V indicating the ADC is not being held in reset. If this is not the case the EVM can be damaged or broken.
ADC Link fails to come up
  • In FPGA tab of the ADC EVM GUI there are a number of LEDs to indicate the FPGAs status. Refer to this and the corresponding table entries below.
FPGA Connect LED not lit up See above table

Entry "TI Capture Card cannot connect in GSPS FPGA Server Application"
FPGA Programmed LED not lit up
  • Verify that power supply meets the criteria of 6V, 5A. Programming the FPGA is one of the highest current draws on the FPGA. Check that during this time the power supply is not hitting its current compliance.
FPGA PLLs Unlocked
  • Verify that EVM hardware is setup as shown in Section 2.7and reference clock to the EVM is at least 9dBm and the frequency matches what is selected in the GUI for the ADC sample frequency.
  • Verify that ADC Clock and reference clock are phase locked to each other.
  • Using Oscilloscope probe on resistor R62 and make sure that frequency matches what is shown in the ADC EVM GUI in the Bringup>JESD tab in the “FPGA Ref Clock” box.
ADC Lanes Unlocked
  • Verify that programmed JESD params in the GSPS FPGA Server match what is shown in the ADC EVM GUI in the Bringup>JESD tab.
  • Probe resistor R204 and make sure that ADC SYSREF signal is present and matches the frequency shown in the Bringup>JESD tab in the “SYSREF” box.
  • Make sure that that jumper J38 is un installed, this verifies that the SYSREF signal is coming from the onboard LMK and not the smp connectors.
ADC Lanes Lock but release delay is stuck at zero
  • Probe resistor R204 and make sure that ADC SYSREF signal is present and matches the frequency shown in the Bringup>JESD tab in the “SYSREF” box.
  • Make sure that jumper J38 is un installed, this makes sure that the SYSREF signal is coming from the onboard LMK and not the smp connectors.
  • Make sure that jumper J27 and J26 are installed, Jumper J25 is uninstalled and SW2 is in the “UP” position.
ADC Lane Buffer Overflow
  • Probe resistor R204 and make sure that ADC SYSREF signal is present and matches the frequency shown in the Bringup>JESD tab in the “SYSREF” box.
  • Make sure that jumper J38 is uninstalled. This verifies that the SYSREF signal is coming from the onboard LMK and not the smp connectors.
  • Verify that ADC Clock and reference clock are phase locked to each other.
Sub Optimal Performance
  • Verify signal quality of both clock and ADC inputs as these directly limit the ADCs performance.
  • Make sure that the bandpass filters are used for both ADC clock and any inputs.