SLVUDB9 July   2025 ADC34RF72

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware and Software Setup
    1. 2.1  Board Overview
    2. 2.2  Required Equipment
    3. 2.3  Required Software Installation
    4. 2.4  Required TI Software to Install
    5. 2.5  3rd Party Software to Install
    6. 2.6  Software Environment Setup
    7. 2.7  Hardware Setup and Connections
    8. 2.8  ADC3xRF72 EVM Connections
    9. 2.9  TSW14J58 Data Capture Card Connections
    10. 2.10 Debug LEDs
    11. 2.11 EVM Jumpers and Switches
  9. 3ADC3xRF72 EVM Configuration and Programming
    1. 3.1  ADC EVM Quick Start
    2. 3.2  Power on all Boards and Signal Generators
    3. 3.3  Launch GSPS FPGA Server
    4. 3.4  Launch High-Speed Data Converter Professional (HSDC Pro) SW
    5. 3.5  Programming the ADC
    6. 3.6  Quick Start Mode
    7. 3.7  System Level Configuration Mode
    8. 3.8  Advanced Mode
    9. 3.9  Runtime Configuration
    10. 3.10 Exporting ADC3xRF72 Configuration and Python API usage
    11. 3.11 Further GUI Help
  10. 4Troubleshooting and FAQ
  11. 5Important Signal Routing
    1. 5.1 ADC Device Clock Routing
    2. 5.2 Board Modifications
      1. 5.2.1 ADC3xRF72 Analog Inputs
  12. 6Hardware Design Files
    1. 6.1 Schematics
    2. 6.2 PCB Layouts
    3. 6.3 Bill of Materials (BOM)
  13. 7Additional Information
    1. 7.1 Trademarks
  14. 8References

2.8 ADC3xRF72 EVM Connections

This section describes all of the necessary connections on the ADC3xRF72 EVM in order. At this time, all power supplies and signal generators must be powered off.

  1. Connect USB mini connector to FTDI Daughter Card.
    1. On connection LED D1 on daughter card lights up green, if not the daughter card can be broken and needs to be inspected.
  2. Connect low-noise signal generator to SMA connector J5 (labeled CLK on EVM), this serves as the high-speed sampling clock to the ADC.
    1. Set Signal generator to desired sampling rate of ADC and output power to 9dBm.
    2. On connection, the signal generator must be in the off state.
  3. Connect low-noise signal generator to SMA connector J12 (labeled LMK CLK on EVM), this serves as the reference clock source to the ADC EVM.
    1. Set Signal generator to match the sampling rate of the device and the output power to 9dBm.
    2. On connection the signal generator must be in the off state.
  4. Connect low-noise signal generator to SMA connector J1 (labeled INA on EVM), this serves as the analog input signal to channel A of the ADC.
  5. Connect 12V 5A to barrel connector J31.
  6. Power on all signal generators to EVM.
  7. Verify that all signal generators are also phase locked to each other.

For best performance TI recommends the use of Bandpass filter for the ADC clock input signals and ADC Analog input signals, this is to help limit the addition of external noise to the ADC.

There are a number of jumper and switches on the EVM for advanced control and extended features. For more information, Section 2.11. For default operation of the EVM, the switches and jumpers they must be in the following configuration:

  • J19 installed: to power DVDDMEM09 ADC power rail from on board DVDD09 rail
  • J20 installed on second option: Installed to set GPIOVDD level to 1.8V
  • J24 installed: Installed to set ADC and LMK SPI control to come from USB via FTDI chip
  • J25 uninstalled: Sets GPIO0, GPIO1 and PDN_ADC to come from FPGA via FMC connector
  • J26 installed: Set range of GPIO to come from USB
  • J27 installed: Set range of GPIO to come from USB
  • J30 installed: Controls Level Shifting direction
  • J34 installed: Selects FPGA Transceiver reference clock to be supplied by the on board LMK04828 device
  • J38 uninstalled: Selects the source of the ADC’s SYSREF signal to come from LMK04828 device
  • J40 installed: Selects the JESDCLKIN input of the ADC to come from the onboard LMK04828 device
  • J45 installed: Selects the HW reset signal for the ADC to be triggered via the USB
  • SW2 UP
  • SW3,4,6 DOWN