SNAS849A December   2024  – July 2026 LMX2624-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Determining the VCO Gain
        3. 6.3.7.3 Double Buffering (Shadow Registers)
        4. 6.3.7.4 Watchdog Feature
        5. 6.3.7.5 RECAL Feature
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Phase Synchronization
        1. 6.3.13.1 General Concept
        2. 6.3.13.2 Categories of Applications for SYNC
        3. 6.3.13.3 Procedure for Using SYNC
      14. 6.3.14 SYSREF
        1. 6.3.14.1 Programmable Fields
        2. 6.3.14.2 Examples
        3. 6.3.14.3 SYSREF Procedure
      15. 6.3.15 Pin-Mode Integer Frequency Generation
        1. 6.3.15.1 4-level Pins Using GPIOs
        2. 6.3.15.2 Pin-Mode Example
      16. 6.3.16 Device Functional Modes
    4. 6.4 Treatment of Unused Pins
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
      3. 6.5.3 Register Maps
        1. 6.5.3.1 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-ended Termination of Unused Output
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Footprint Example on PCB Layout
      4. 7.4.4 Radiation Environments
        1. 7.4.4.1 Total Ionizing Dose
        2. 7.4.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Engineering Samples
    2. 10.2 Package Option Addendum
    3. 10.3 Tape and Reel Information

6.5.3 Register Maps

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 VCO_PHASE_SYNC 1 FCAL_DBLR_EN 0 0 OUT_MUTE FCAL_HPFD_ADJ FCAL_LPFD_ADJ 1 FCAL_EN RESET POWERDOWN
R1 0 MASH_SEED_EN READBACK LD_TYPE OUTB_MUTE_POL OUTA_MUTE_POL OUTB_MUTE_PIN OUTA_MUTE_PIN OUTB_MUTE OUTA_MUTE OUTB_PD OUTA_PD 1 CAL_CLK_DIV
R2 0 0 0 0 1 CPG 0 0 OUTB_PWR OUTA_PWR
R3 OUTB_MUX OUTA_MUX OUTMUX PFD_DLY CHDIV
R4 0 VCO_CAPCTRL_FORCE VCO_DACISET_FORCE VCO_SEL_FORCE QUICK_RECAL_EN 1 1 0 0 1 0 0 0 1 0 0
R5 MASH_ORDER VCO_FULL_ASSIST VCO_SEL VCO_DACISET
R6 0 DBLR_AMP1_DACCTRL DBLR_AMP_CAPCTRL DBLR1_PD VCO_CAPCTRL
R7 0 VCO_FASTCHG_CNT DBLR_PG_AMP_DACCTRL DBLR_PG_AMP_CAPCTRL
R8 PLL_N
R9 PLL_N[18:16] 0 0 0 0 0 0 0 0 0 0 0 0 0
R10 PLL_DEN[15:0]
R11 PLL_DEN[31:16]
R12 MASH_SEED[15:0]
R13 MASH_SEED[31:16]
R14 PLL_NUM[15:0]
R15 PLL_NUM[31:16]
R16 0 0 0 0 0 0 0 DBL_BUF_EN PLL_R
R17 0 0 0 OSC_2X PLL_R_PRE
R18 SYSREF_DIV SYSREF_DIV_PRE SYSREF_EN SYSREF_REPEAT
R19 0 JESD_DAC2 JESD_DAC1 RPTR_NONSYNC 0 SYSREF_PULSE
R20 SYSREF_PULSE_CNT JESD_DAC4 JESD_DAC3
R22 0 0 0 0 0 0 0 0 0 MUXOUT
R23 LD_DLY
R30 MASH_RST_COUNT[15:0]
R31 MASH_RST_COUNT[31:16]
R32 0 0 0 0 0 0 WD_DLY WD_CNTRL
R34 rb_VER_ID
R35 0 0 0 0 0 0 0 0 0 0 rb_LD_VTUNE rb_VCO_SEL 0
R84 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0