SNAS849A December   2024  – July 2026 LMX2624-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Determining the VCO Gain
        3. 6.3.7.3 Double Buffering (Shadow Registers)
        4. 6.3.7.4 Watchdog Feature
        5. 6.3.7.5 RECAL Feature
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Phase Synchronization
        1. 6.3.13.1 General Concept
        2. 6.3.13.2 Categories of Applications for SYNC
        3. 6.3.13.3 Procedure for Using SYNC
      14. 6.3.14 SYSREF
        1. 6.3.14.1 Programmable Fields
        2. 6.3.14.2 Examples
        3. 6.3.14.3 SYSREF Procedure
      15. 6.3.15 Pin-Mode Integer Frequency Generation
        1. 6.3.15.1 4-level Pins Using GPIOs
        2. 6.3.15.2 Pin-Mode Example
      16. 6.3.16 Device Functional Modes
    4. 6.4 Treatment of Unused Pins
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
      3. 6.5.3 Register Maps
        1. 6.5.3.1 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-ended Termination of Unused Output
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Footprint Example on PCB Layout
      4. 7.4.4 Radiation Environments
        1. 7.4.4.1 Total Ionizing Dose
        2. 7.4.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Engineering Samples
    2. 10.2 Package Option Addendum
    3. 10.3 Tape and Reel Information

6.3.8 Channel Divider

To go below the VCO lower bound of 7500MHz, the channel divider can be used. The channel divider utilizes three stages with a total division ratio equal to the product of the three dividers.. Therefore, not all values are valid.

LMX2624-SP Channel Divider Figure 6-2 Channel Divider

When the channel divider is used, there are limitations on the values. Table 6-9 shows how these values are implemented.

Table 6-9 Channel Divider Segments
EQUIVALENT DIVISION VALUE FREQUENCY LIMITATION OutMin (MHz) OutMax (MHz) CHDIV[4:0]
2 None 3750 7500 1
4 1875 3750 2
6 fVCO ≤ 12GHz 1250 2000 3
8 937.5 1500 4
12 625 1000 5
16 468.75 750 6
24 312.5 500 7
32 234.375 375 8
48 156.25 250 9
64 117.1875 187.5 10
96 78.125 125 11
128 58.59375 93.75 12
192 39.0625 62.5 13
256 29.296875 46.875 14
384 19.53125 31.25 15
512 14.6484375 23.4375 16
768 9.765625 15.625 17
1024 7.32421875 11.71875 18
1536 4.8828125 7.8125 19

The channel divider is powered up whenever an output (OUTx_MUX) is selected to the channel divider or SysRef, regardless of whether the output is powered down or not. When an output is not used, TI recommends selecting the VCO output to verify that the channel divider is not unnecessarily powered up.

Table 6-10 Channel Divider
RFOUTA RFOUTB CHANNEL DIVIDER Status
Channel Divider Channel Divider Powered up
Channel Divider VCO Powered up
VCO Channel Divider Powered up
Doubler Channel Divider Powered up
VCO VCO Powered down
VCO Doubler Powered down
Doubler VCO Powered down
Doubler Doubler Powered down