SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

4.1 Auto-Scrolling Configuration

This example configures the Pattern Generator to scroll through a sequence of Red, Green, Blue, with each pattern displayed for 60 video frames, using external timing:

  1. Write 0x1E to the PGFT register (Table 3-21). This sets the frame timer to 60.
  2. Write 0x03 to the PGTSC register (Table 3-22). This sets the number of active patterns to 3.
  3. Write 0x43 to the PGTSO1 register (Table 3-23). This sets Pattern 1 to Red (3) and Pattern 2 to Green (4).
  4. Write 0x05 to the PGTSO2 register (Table 3-24). This sets Pattern 3 to Blue (5); Pattern 4 is ignored.
  5. Write 0x01 to the PGCFG register (Table 3-1) to enable Auto-Scrolling with external timing.
  6. Write 0x01 to the PGCTL register (Table 3-1) to enable the pattern generator.