5 - 85 MHz 24-bit Color FPD-Link III Serializer with HDCP



Product details


Function Serializer Color depth (bpp) 24 Pixel clock frequency (Min) (MHz) 5 Pixel clock frequency (Max) (MHz) 85 Input compatibility LVCMOS Output compatibility FPD-Link III LVDS Features HDCP, I2C Config, I2S Audio Signal conditioning DC Balance EMI reduction SSC Compatible Diagnostics BIST Throughput (Mbps) 2040 Operating temperature range (C) -40 to 105 open-in-new Find other Display SerDes

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Display SerDes


  • Integrated HDCP Cipher Engine with On-chip Key
  • Bidirectional Control Interface Channel Interface
    with I2C Compatible Serial Control Bus
  • Supports High Definition (720p) Digital Video
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • 5 to 85 MHz PCLK Supported
  • Single 3.3V Operation with 1.8 V or 3.3 V Compatible
    LVCMOS I/O Interface
  • AC-coupled STP Interconnect up to 10 meters
  • Parallel LVCMOS Video Inputs
  • DC-balanced & Scrambled Data with Embedded
  • HDCP Content Protected
  • Supports HDCP Repeater Application
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • > 8k V HBM and ISO 10605 ESD rating
  • Backward Compatible Modes
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The DS90UH925Q-Q1 serializer, in conjunction with the DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH925Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.

EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.

The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.

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Same functionality but is not pin-for-pin or parametrically equivalent to the compared device:
DS90UH925AQ-Q1 ACTIVE 5 to 85 MHz 24-bit Color FPD-Link III Serializer with HDCP Similar to DS90UH925Q-Q1 with addition of a local output pin for remote interrupt mirroring from deserializer

Technical documentation

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Type Title Date
* Datasheet DS90UH925Q-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP datasheet (Rev. J) Nov. 07, 2014
Application note Exploring the Int Test Pattern Generation Feature of FPD-Link III IVI Devices (Rev. G) Nov. 03, 2020
Technical articles How to choose a power supply for an automotive camera module Sep. 17, 2020
Application note Enabling GPIOs in DS90UB925 and DS90UB926 Nov. 10, 2015
Application note Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices May 04, 2013
Application note I2C Communication Over FPD-Link III with Bidirectional Control Channel (Rev. A) Apr. 26, 2013
User guide DS90UH925QSEVB User's Guide Sep. 20, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The DS90UH925QSEVB is an evaluation board designed to demonstrate the performance and unique features of the DS90UH925Q FPD-Link III serializer.

The DS90UH925QSEVB board is designed to drive any of TI’s compatible FPD-Link III deserializer devices. The LVCMOS inputs of the DS90UH925Q are accessible (...)

  • Converts parallel LVCMOS to FPD-Link III serialized data stream
  • Built-in internal oscillator and pattern generator for standalone operation
  • Includes I2C tool for easy device configuration
  • Interoperates with compatible FPD-Link III Deserializers

Design tools & simulation

SNLM118.ZIP (67 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

Reference designs

Automotive TFT LCD Display Solution
TIDA-00169 This reference design implements a video over LVDS solution for automotive infotainment applications.It highlights the support of multi-touch with haptic feedback, LCD backlight control, and ambient light sensing, without the introduction of dedicated support lines back to the host processor. This (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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WQFN (RHS) 48 View options

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