SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

3.2.2 Internal Timing Control

The Internal Timing Control registers configure the generated pixel clock frequency and video frame parameters for internal timing mode. The default values are configured for 800x480 resolution at 61.4Hz as shown in the following Table 3-8.

Table 3-8 Internal Timing Default Values
ParameterDefaultUnits
Clock Divider8-
Refresh Rate61.4Hz
Total Horizontal Width840Pixels
Total Vertical Width485Lines
Active Horizontal Width800Pixels
Active Vertical Width480Lines
Horizontal Sync Width10Pixels
Vertical Sync Width2Lines
Horizontal Back Porch10Pixels
Vertical Back Porch2Lines
Horizontal Sync PolarityNegativeN/A
Vertical Sync PolarityNegativeN/A

Pattern Generator Clock Divider N Configuration (PGCDC1), address 0x03 in Table 3-4.

This register controls the N divider for the internal clock when the internal pixel clock is selected. For all devices besides DS90Ux941AS-Q1, DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1, the M clock divider value is assumed to be 1.

Table 3-9 Pattern Generator Clock Divider N Configuration (PGCDC1)
BitAccessFieldDefault (bin)Description
7:6Reserved00Reserved. Reads return 0, writes are ignored.
5:0RWPATGEN_CDIV_N001000Clock Divider:
This field configures the "N" clock divider for the internal 200 MHz clock when the pattern generator uses internal timing. Valid values are 2 through 63; values 0 and 1 are reserved and must not be used.

Pattern Generator Total Frame Size 1 (PGTFS1), address 0x04 in Table 3-4.

This register, along with the Total Frame Size 2 register, configures the Total Horizontal Width of the frame. The value in this register is used when internal video timing is enabled.

Table 3-10 Pattern Generator Total Frame Size 1 (PGTFS1)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_THW01001000Total Horizontal Width:
This field is the 8 least significant bits of the 12-bit Total Horizontal Width of the frame, in units of pixels. This field should only be written when the pattern generator is disabled.

Pattern Generator Total Frame Size 2 (PGTFS2), address 0x05 in Table 3-4.

This register, along with the Total Frame Size 1 register, configures the Total Horizontal Width of the frame. In addition, along with the Total Frame Size 3 register, this register configures the Total Vertical Width of the frame. The values in this register are used when internal video timing is enabled.

Table 3-11 Pattern Generator Total Frame Size 2 (PGTFS2)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TVW0101Total Vertical Width:
This field is the 4 least significant bits of the 12-bit Total Vertical Width of the frame, in units of lines. This field should only be written when the pattern generator is disabled.
3:0RWPATGEN_THW0011Total Horizontal Width:
This field is the 4 most significant bits of the 12-bit Total Horizontal Width of the frame, in units of pixels. This field should only be written when the pattern generator is disabled.

Pattern Generator Total Frame Size 3 (PGTFS3), address 0x06 in Table 3-4.

This register, along with the Total Frame Size 2 register, configures the Total Vertical Width of the frame. The values in this register are used when internal video timing is enabled.

Table 3-12 Pattern Generator Total Frame Size 3 (PGTFS3)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_TVW00011110Total Vertical Width:
This field is the 8 most significant bits of the 12-bit Total Vertical Width of the frame, in units of lines. This field should only be written when the pattern generator is disabled.

Pattern Generator Active Frame Size 1 (PGAFS1), address 0x07 in Table 3-4.

This register, along with the Active Frame Size 2 register, configures the Active Horizontal Width of the frame. The value in this register is used when internal video timing is enabled.

Table 3-13 Pattern Generator Active Frame Size 1 (PGAFS1)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_AHW00100000Active Horizontal Width:
This field is the 8 least significant bits of the 12-bit Active Horizontal Width of the frame, in units of pixels. This field should only be written when the pattern generator is disabled.

Pattern Generator Active Frame Size 2 (PGAFS2), address 0x08 in Table 3-4.

This register, along with the Active Frame Size 1 register, configures the Active Horizontal Width of the frame. In addition, along with the Active Frame Size 3 register, this register configures the Active Vertical Width of the frame. The values in this register are used when internal video timing is enabled.

Table 3-14 Pattern Generator Active Frame Size 2 (PGAFS2)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_AVW0000Active Vertical Width:
This field is the 4 least significant bits of the 12-bit Active Vertical Width of the frame, in units of lines. This field should only be written when the pattern generator is disabled.
3:0RWPATGEN_AHW0011Active Horizontal Width:
This field is the 4 most significant bits of the 12-bit Active Horizontal Width of the frame, in units of pixels. This field should only be written when the pattern generator is disabled.

Pattern Generator Active Frame Size 3 (PGAFS3), address 0x09 in Table 3-4.

This register, along with the Active Frame Size 2 register, configures the Active Vertical Width of the frame. The value in this register is used when internal video timing is enabled.

Table 3-15 Pattern Generator Active Frame Size 3 (PGAFS3)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_AVW00011110Active Vertical Width:
This field is the 8 most significant bits of the 12-bit Active Vertical Width of the frame, in units of lines. This field should only be written when the pattern generator is disabled.

Pattern Generator Horizontal Sync Width (PGHSW), address 0x0A in Table 3-4.

This register configures the Horizontal Sync Width of the frame. The value in this register is used when internal video timing is enabled.

Table 3-16 Pattern Generator Horizontal Sync Width (PGHSW)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_HSW00001010Horizontal Sync Width:
This field controls the width of the Horizontal Sync pulse, in units of pixels. Valid values are 1-255. This field should only be written when the pattern generator is disabled.

Pattern Generator Vertical Sync Width (PGVSW), address 0x0B in Table 3-4.

This register configures the Vertical Sync Width of the frame. The value in this register is used when internal video timing is enabled.

Table 3-17 Pattern Generator Vertical Sync Width (PGVSW)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_VSW00000010Vertical Sync Width:
This field controls the width of the Vertical Sync pulse, in units of lines. Valid values are 1-255. This field should only be written when the pattern generator is disabled.

Pattern Generator Horizontal Back Porch (PGHBP), address 0x0C in Table 3-4.

This register configures the width of the Horizontal Back Porch of the frame. The value in this register is used when internal video timing is enabled.

Table 3-18 Pattern Generator Horizontal Back Porch (PGHBP)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_HBP00001010Horizontal Back Porch Width:
This field controls the width of the Horizontal Back Porch, in units of pixels. Valid values are 1-255. This field should only be written when the pattern generator is disabled.

Pattern Generator Vertical Back Porch (PGVBP), address 0x0D in Table 3-4.

This register configures the width of the Horizontal Back Porch of the frame. The value in this register is used when internal video timing is enabled.

Table 3-19 Pattern Generator Vertical Back Porch (PGVBP)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_VBP00000010Vertical Back Porch Width:
This field controls the width of the Vertical Back Porch, in units of lines. Valid values are 1-255. This field should only be written when the pattern generator is disabled.

Pattern Generator Sync Configuration (PGSC), address 0x0E in Table 3-4.

This register configures the generator of Horizontal and Vertical Sync signaling.

Table 3-20 Pattern Generator Sync Configuration (PGSC)
BitAccessFieldDefault (bin)Description
7:4Reserved0000Reserved:
Reads return 0, writes are ignored.
3RWPATGEN_VS_DIS0Vertical Sync Disable:
Disable Vertical Sync signaling when the pattern generator is in internal timing mode. This bit has no effect when the pattern generator is in external timing mode. This bit should only be written when the pattern generator is disabled.
2RWPATGEN_HS_DIS0Horizontal Sync Disable:
Disable Horizontal Sync signaling when the pattern generator is in internal timing mode. This bit has no effect when the pattern generator is in external timing mode. This bit should only be written when the pattern generator is disabled.
1RWPATGEN_VS_POL1Vertical Sync Polarity:
When 1, the pattern generator will invert the Vertical Sync signal when in internal timing mode. This bit has no effect when the pattern generator is in external timing mode. This bit should only be written when the pattern generator is disabled.
0RWPATGEN_HS_POL1Horizontal Sync Polarity:
When 1, the pattern generator will invert the Horizontal Sync signal when in internal timing mode. This bit has no effect when the pattern generator is in external timing mode. This bit should only be written when the pattern generator is disabled.