SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

3.4 QepDiv CLB Configuration

The PTO API implementation source files are located under [C2000Ware_MotorControl_SDK]\libraries\position_sensing\pto\source.

The following resources are used inside the CLB tile to achieve the desired function detailed in Section 3.1.

GUID-C6E65D1A-1EF3-48BD-B1DA-CED98AD1E1F7-low.gif Figure 3-4 QepDiv CLB Tile Diagram
Note: You can import and build the QepDiv API reference project for each respective device, located in [C2000Ware_MotorControl_SDK]\libraries\position_sensing\pto\ccs. By rebuilding the compiled object, it will regenerate the CLB tile diagram (clb.svg or clb.html). and object (.lib) The CLB tile diagram will be located in the RELEASE/syscfg directory.

Implementation is described in detail, below and visualized in Figure 3-4.

Table 3-1 QepDiv CLB Tile 1
Resource Function Notes
Inputs
In0 On/Off Control via GPREG Enable CLB
In1 On/Off Control via GPREG QEPA via EPWM4A
In2 Edge Detect QEPA via EPWM4A
In3 Not used Not used
In4 On/Off Control via GPREG QEPB via EPWM5A
In5 Edge Detect QEPB via EPWM5A
In6 Not used Not used
In7 Edge Detect QEPI via EPWM4B
Outputs
Out0 Not used Not used
Out1 Not used Not used
Out2 Not used Not used
Out3 Not used Not used
Out4 Transmit Enable PTO Direction Via OUTPUT XBar; Input for CLB 2
Out5 Transmit Enable QEPI output via OUTPUTXBAR3
Out6 Not used Not used
Out7 Not used Not used
Logic Resources
LUT0 Not used Not used
LUT1 Determines QCLK direction in combo with FSM0 and FSM1 Provides input to FSM1 for external input 0
LUT2 Not used Not used
FSM0 Alternate inputs between QEPA and QEPB This state machine checks the QEP signals and alternates between the different signals
FSM1 Set QCLK direction Uses output of LUT1 and FSM0 to set up the QCLK, which in turn sets the direction. The output will be routed to CLB2 as the input direction
FSM2 Index pulse generation Takes the QEPI input and uses CNT2 Match2 value to set the QEPI output period and duty cycle.
CNT0 Set index pulse width value Load indexWidth-1 value set via CLB_writeInterface function
CNT1 Set divider value Load divider*4 value set via CLB_writeInterface function
CNT2 Set divide value Load divider*2 value set via CLB_writeInterface function
High Level Controller
HLC Not used Not used
Table 3-2 QepDiv CLB Tile 2
Resource Function Notes
Inputs
In0 On/Off Control via GPREG Enable CLB
In1 On/Off Control via GPREG QEPA via EPWM4A
In2 Edge Detect QEPA via EPWM4A
In3 Not used Not used
In4 Edge Detect QEPB via EPWM5A
In5 Not used Not used
In6 Not used Not used
In7 On/Off Control via GPREG PTO direction routed from CLB1 out4
Outputs
Out0 Transmit Enable QEPA Output via EPWM2A
Out1 Not used Not used
Out2 Transmit Enable QEPB Output via EPWM2B
Out3 Not used Not used
Out4 Transmit Enable Bypass Logic
Out5 Not used Not used
Out6 Not used Not used
Out7 Not used Not used
Logic Resources
LUT0 QEPA/QEPB signal input When the tile is on, send the selected QEP signal to CNT0 as mode0 input
LUT1 Generate high and low values for Alternate between high and low
LUT2 Not used Not used
FSM0 QEP Pulse width generation This state machine together with CNT0 will generate a number of hi and low pulse widths for LUT1 and LUT2.
FSM1 QEPA signal generation Generates QEPA output using CNT0 and LUT1.
FSM2 QEPB signal generation Generates QEPB output using CNT0 and LUT2.
CNT0 Counter for output QEP signal generation Counter Match1 value is the external input for FSM0. Match2 value is the reset value for the counter. The match2 value is passed to LUT1 and LUT2 .
CNT1 Not used Not used
CNT2 Not used Not used
High Level Controller
HLC Not used Not used