SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

2.3 PulseGen CLB Configuration

The following resources are used inside the CLB tile to achieve the desired function detailed in Section 2.1.

GUID-027B71BB-2E5A-4862-B3B0-CEA6B25D1803-low.gif Figure 2-3 PulseGen CLB Tile Diagram
Note: Section 7 describes how to build the library project in Code Composer Studio™. By building the project, CCS will regenerate the CLB tile diagram (clb.svg or clb.html). and object (.lib). The CLB tile diagram will be located in the RELEASE/syscfg directory.

Implementation is described in Table 2-1 and visualized in Figure 2-3.

Table 2-1 PulseGen CLB Tile 1
Resource Function Notes
Inputs
In0 On/Off Control via GPREG Enable CLB
In1 Rising Edge Detect Via EPWM1A
In2 On/Off Control via GPREG Run signal (start/stop of PTO)
In3 Not used Not used
In4 On/Off Control via GPREG Sets the PTO direction
In5 Not used Not used
In6 Not used Not used
In7 Not used Not used
Outputs
Out0 Not used Not used
Out1 Not used Not used
Out2 Not used Not used
Out3 Not used Not used
Out4 Transmit Enable Via OUTPUT XBar; PTO pulse output
Out5 Transmit Enable Via OUTPUT XBar; PTO direction output
Out6 Not used Not used
Out7 Not used Not used
Logic Resources
LUT0 Input for Event0 in HLC Edge detection on encoder input with either in1 or CNT1 match value. Triggers event in HLC to load new values into HLC registers
LUT1 Mode0 input for CNTs 1,2,3 Logic to determine the selected modes for CNT1, CNT2, and CNT3. Starts all three counters.
LUT2 Not used Not used
FSM0 Pulse width generation This state machine together with CNT0 will generate a number of hi and low pulse widths. The output sets the reset value of CNT0.
FSM1 Active and Full Period generation Sets the values for the active and full period based on match1 and match2 outputs of CNT1. Outputs number of pulses in active period duration and none in between the difference of the full and active periods
FSM2 PTO output direction generation Generates the PTO output direction. The output direction is held until the end of the full period set by FSM1.
CNT0 Pulse width generation Counter Match1 and Match2 values determine triggers for hi and low pulse widths. The match values are loaded to FSM0 inputs, e0 and e1.
CNT1 Active and Full Period Clock generation Generates inputs needed for FSM1 and FSM2. Match1 determines trigger for active period. Match2 determines trigger for full period. Match events are used by FSM1 to generate active and full periods. Match2 is used as extra external input in FSM0 to determine how long to hold PTO output direction.
CNT2 Counter for full period Match1 event used to trigger interrupt in HLC. Counter is reset when full period of signal is reached
High Level Controller
HLC Event0 used to trigger taskEvent1 used to trigger interrupt Event0 used to load new options for the PTO from C28 core into CLBEvent1 used to generate an interrupt based on match1 event of CNT2, which corresponds to the full period. New PTO options take effect after this event.