SPRADP2 January   2025 AWR1843 , AWR2544 , AWR2944 , AWR2944P

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2ADAS Radar Market Trends and Evolution of Requirements
  5. 3AWR2E44P and AWR2944P - Performance, Processing, and Memory Enhancements
    1. 3.1 Signal-to-Noise Ratio (SNR) Improvement
    2. 3.2 TI 2nd Generation Launch on Package Technology (LOP)
    3. 3.3 Increased Computational Capacity
    4. 3.4 Expanded Memory for Radar Data Cube
    5. 3.5 1Gbps Ethernet Interface
    6. 3.6 Enhanced Security and Reliability
    7. 3.7 eBOM Optimization
  6. 4No Compromise on SW Scalability and Reusability
    1. 4.1 Software Development Kit
    2. 4.2 Microcontroller Abstraction Layer
    3. 4.3 mmWave DFP (Device Firmware Package)
    4. 4.4 TI Foundational Security
    5. 4.5 Safety Diagnostic Library
  7. 5AWR2E44P Evaluation and Measurements
  8. 6Summary
  9. 7Acknowledgments

3 AWR2E44P and AWR2944P - Performance, Processing, and Memory Enhancements

The AWR2E44P and AWR2944P are performance enhanced relative to the AWR2944 product family, with enhancements to RF performance and compute capacity to meet NCAP and AD requirements. Figure 3-1 shows a block diagram of AWR2E44P/AWR2944P architecture. These devices are both single chip 76-81GHz FMCW radar sensor and include:

  • 4 integrated transmitters
  • 4 integrated receivers
  • Calibration engines
  • Monitoring engines
  • Synthesizer
  • C66x DSP
  • Hardware security module (HSM)
  • Hardware accelerator (HWA)
  • Memory
  • Interfaces
AWR2944P, AWR2E44P AWR2E44P / AWR2944P block diagramFigure 3-1 AWR2E44P / AWR2944P block diagram

AWR2E44P and AWR2944P offer an improvement in overall sensor SNR, enhanced compute capabilities, increased memory, uses TI second generation LoP, enables 10x higher data transfer rate, HSM improvement and eBOM (electronic bill of material) optimization.