The following patch applies on top of commit: f3f8c664b300 ("PSTREAM: board: ti: common: Kconfig: add CMD_CACHE")

0001-arm-mach-k3-j784s4-Remove-priority-equalization-and-.patch

From 7ac3b82eca22d6d28ca767d400c8aa5830704a59 Mon Sep 17 00:00:00 2001
From: Jared McArthur <j-mcarthur@ti.com>
Date: Thu, 28 Aug 2025 17:35:44 -0500
Subject: [PATCH 1/1] arm: mach-k3: j784s4: Remove priority equalization and
 honor VBUSM priorities

Give the DDR controller's high priority thread (HPT) priority over the
low priority thread (LPT) and give weight to transactions' individual
priorities as well.

By default, the J784S4's MSMC2DDR bridge maps all VBUSM priorities to
0. This is done with priority mapping registers.

DDRSSX_V2A_LPT_DEF_PRI_MAP_REG: default VBUSM to DDR controller
priority mapping for LPT

DDRSSX_V2A_HPT_DEF_PRI_MAP_REG: default VBUSM to DDR controller
priority mapping for HPT

Set DDRSSX_V2A_LPT_DEF_PRI_MAP_REG as 0x23456677 and
DDRSSX_V2A_HPT_DEF_PRI_MAP_REG as 0x00112345. The values are taken
from the default values for the J721E [0] and are also the default values
for the J784S4 priority map range muxes [1].

[0] https://www.ti.com/lit/zip/spruil1
[1] https://www.ti.com/lit/zip/spruj52

Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
---
 arch/arm/mach-k3/j784s4/j784s4_init.c | 35 +++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 9897f4fb921..f66a8fd1774 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -45,6 +45,27 @@
 #define NB_THREADMAP_BIT1				BIT(1)
 #define NB_THREADMAP_BIT2				BIT(2)
 
+/* DDRSS Config */
+#define DDRSS0_EMIF_EW_SSCFG		0x02980000
+#define DDRSS1_EMIF_EW_SSCFG		0x029A0000
+#define DDRSS2_EMIF_EW_SSCFG		0x029C0000
+#define DDRSS3_EMIF_EW_SSCFG		0x029E0000
+#define DDRSS0_V2A_LPT_DEF_PRI_MAP_REG	(DDRSS0_EMIF_EW_SSCFG + 0x30)
+#define DDRSS0_V2A_HPT_DEF_PRI_MAP_REG	(DDRSS0_EMIF_EW_SSCFG + 0x4C)
+#define DDRSS1_V2A_LPT_DEF_PRI_MAP_REG	(DDRSS1_EMIF_EW_SSCFG + 0x30)
+#define DDRSS1_V2A_HPT_DEF_PRI_MAP_REG	(DDRSS1_EMIF_EW_SSCFG + 0x4C)
+#define DDRSS2_V2A_LPT_DEF_PRI_MAP_REG	(DDRSS2_EMIF_EW_SSCFG + 0x30)
+#define DDRSS2_V2A_HPT_DEF_PRI_MAP_REG	(DDRSS2_EMIF_EW_SSCFG + 0x4C)
+#define DDRSS3_V2A_LPT_DEF_PRI_MAP_REG	(DDRSS3_EMIF_EW_SSCFG + 0x30)
+#define DDRSS3_V2A_HPT_DEF_PRI_MAP_REG	(DDRSS3_EMIF_EW_SSCFG + 0x4C)
+
+/*
+ * New thread priority mapping to remove complete priority equalization
+ * of threads coming from VBUSM space to DDRSS space.
+ */
+#define DDRSS_V2A_LPT_DEF_PRIMAP	0x23456677
+#define DDRSS_V2A_HPT_DEF_PRIMAP	0x00112345
+
 struct fwl_data infra_cbass0_fwls[] = {
 	{ "PSC0", 5, 1 },
 	{ "PLL_CTRL0", 6, 1 },
@@ -123,6 +144,19 @@ static void setup_navss_nb(void)
 	writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
 }
 
+/* Setup DDRSS CoS (Class of Service) registers to remove priority equalization */
+static void setup_ddrss_cos(void)
+{
+	writel(DDRSS_V2A_LPT_DEF_PRIMAP, (uintptr_t)DDRSS0_V2A_LPT_DEF_PRI_MAP_REG);
+	writel(DDRSS_V2A_HPT_DEF_PRIMAP, (uintptr_t)DDRSS0_V2A_HPT_DEF_PRI_MAP_REG);
+	writel(DDRSS_V2A_LPT_DEF_PRIMAP, (uintptr_t)DDRSS1_V2A_LPT_DEF_PRI_MAP_REG);
+	writel(DDRSS_V2A_HPT_DEF_PRIMAP, (uintptr_t)DDRSS1_V2A_HPT_DEF_PRI_MAP_REG);
+	writel(DDRSS_V2A_LPT_DEF_PRIMAP, (uintptr_t)DDRSS2_V2A_LPT_DEF_PRI_MAP_REG);
+	writel(DDRSS_V2A_HPT_DEF_PRIMAP, (uintptr_t)DDRSS2_V2A_HPT_DEF_PRI_MAP_REG);
+	writel(DDRSS_V2A_LPT_DEF_PRIMAP, (uintptr_t)DDRSS3_V2A_LPT_DEF_PRI_MAP_REG);
+	writel(DDRSS_V2A_HPT_DEF_PRIMAP, (uintptr_t)DDRSS3_V2A_HPT_DEF_PRI_MAP_REG);
+}
+
 /* Execute and check results of BIST executed on MCU1_x and MCU4_O */
 static void run_bist_j784s4(struct udevice *dev)
 {
@@ -328,6 +362,7 @@ void board_init_f(ulong dummy)
 		setup_navss_nb();
 
 	setup_qos();
+	setup_ddrss_cos();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
-- 
2.34.1