SPRADS6A March   2026  – March 2026 AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Data Movement within the TDA4VH
    1. 1.1 Common Bus Architecture Subsystem (CBASS)
    2. 1.2 Navigator Subsystems (NAVSS)
      1. 1.2.1 NAVSS North Bridge (NB)
    3. 1.3 Multicore Shared Memory Controller (MSMC)
  5. 2Quality of Service (QoS)
    1. 2.1 NAVSS0
      1. 2.1.1 NAVSS0 North Bridge
        1. 2.1.1.1 Normal vs Real-Time Traffic
    2. 2.2 Multicore Shared Memory Controller (MSMC)
    3. 2.3 DDR Subsystem (DDRSS)
      1. 2.3.1 MSMC2DDR Bridge
      2. 2.3.2 Class of Service (CoS)
    4. 2.4 QoS Summary
  6. 3Case Study: Display Sync Lost Issue
    1. 3.1 Problem Statement
    2. 3.2 Setup and Recreation
      1. 3.2.1 Requirements
        1. 3.2.1.1 RTOS Patches
          1. 3.2.1.1.1 0001-vision_apps-Remove-the-DSS-application-from-MCU2_0.patch
          2. 3.2.1.1.2 0002-vision_apps-Remove-display-use-from-the-AVP-demo.patch
        2. 3.2.1.2 Linux Patches
          1. 3.2.1.2.1 0001-arm64-dts-ti-k3-j784s4-vision-apps-Re-enable-DSS-for.patch
      2. 3.2.2 Host Setup
      3. 3.2.3 Target Setup
      4. 3.2.4 Recreation
    3. 3.3 Debugging QoS
      1. 3.3.1 CPTracer
        1. 3.3.1.1  Setup
        2. 3.3.1.2  Profiling Throughput
        3. 3.3.1.3  Profiling Latency
        4. 3.3.1.4  Profiling Transactions
        5. 3.3.1.5  Profiling Relevant Routes
        6. 3.3.1.6  Profiling DSS Throughput
          1. 3.3.1.6.1 Theoretical DSS Throughput
          2. 3.3.1.6.2 Normal DSS Throughput
          3. 3.3.1.6.3 DSS Throughput with the AVP Demo Running
        7. 3.3.1.7  Profiling DSS Latency
        8. 3.3.1.8  Profiling C7x Throughput
        9. 3.3.1.9  Profiling C7x Throughput vs DSS Latency
        10. 3.3.1.10 Profiling C7x_4 Core Transactions
      2. 3.3.2 Editing QoS Settings
        1. 3.3.2.1 Editing Order ID
          1. 3.3.2.1.1 DSS Order ID
          2. 3.3.2.1.2 C7x Order ID
        2. 3.3.2.2 NRT and RT Routing
          1. 3.3.2.2.1 NRT and RT Routing in U-Boot
        3. 3.3.2.3 Editing Priority
          1. 3.3.2.3.1 DSS Priority
          2. 3.3.2.3.2 C7x Priority
      3. 3.3.3 Editing CoS Mappings
        1. 3.3.3.1 CoS Mapping Registers
        2. 3.3.3.2 Checking CoS Mappings
    4. 3.4 Fixing the DSS Sync Losts
      1. 3.4.1 Remap C7x_4 Core Transactions
        1. 3.4.1.1 ti-u-boot-2023.04
        2. 3.4.1.2 ti-u-boot-2025.01
      2. 3.4.2 Honor All Priorities
        1. 3.4.2.1 ti-u-boot-2023.04
        2. 3.4.2.2 ti-u-boot-2025.01
  7. 4Summary
  8. 5References
  9. 6Revision History

2.1.1.1 Normal vs Real-Time Traffic

The north bridge uses 3 threads to separate traffic to the MSMC:

  • Thread 0: commands to VBUSM.C

  • Thread 1: commands from VBUSM.C

  • Thread 2: real-time commands to VBUSM.C

To support quality of service, the North Bridge provides registers to map the sources to either the normal thread (0) or real-time thread (2). Any source mapped to the real-time thread will be arbitrated before the normal thread. If there are multiple sources mapped to the same thread, then they are arbitrated based on priority, and if they are the same priority, then by round robin. In this way, the North Bridge is able to split traffic and assign priority by order ID (and in a way expand the number of possible priorities).

Programming whether an order ID is mapped to the normal or real-time thread is done within the NAVSS North Bridge MMR registers, specifically within the NAVSS_NORTH_x_NBSS_NBx_MMRS_threadmap (x signifies 0 or 1) register.

Table 2-2 NAVSS North Bridge Threadmap Registers

Register

Field

Bit(s)

Description

NAVSS_NORTH_0_NBSS_NB0_MMRS_threadmap

RESERVED

31:3

Reserved

THREADMAP

1

Maps order IDs 8-15 to a VBUSM.C thread number:

  • 0: VBUSM.C thread 0 (non-real time traffic)

  • 1: VBUSM.C thread 2 (real time traffic)

0

Maps order IDs 0-7 to a VBUSM.C thread number:

  • 0: VBUSM.C thread 0 (non-real time traffic)

  • 1: VBUSM.C thread 2 (real time traffic)

NAVSS_NORTH_1_NBSS_NB1_MMRS_threadmap

RESERVED

31:3

Reserved

THREADMAP

2

Maps order IDs 10-15 to a VBUSM.C thread number:

  • 0: VBUSM.C thread 0 (non-real time traffic)

  • 1: VBUSM.C thread 2 (real time traffic)

1

Maps order IDs 5-9 to a VBUSM.C thread number:

  • 0: VBUSM.C thread 0 (non-real time traffic)

  • 1: VBUSM.C thread 2 (real time traffic)

0

Maps order IDs 0-4 to a VBUSM.C thread number:

  • 0: VBUSM.C thread 0 (non-real time traffic)

  • 1: VBUSM.C thread 2 (real time traffic)

CAUTION:

The NAVSS_NORTH_x_NBSS_NBx_MMRS_threadmap register's fields vary between devices. The above table is representative of the TDA4VH.