SPRUI33H November   2015  – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 Viterbi, Complex Math, and CRC Unit (VCU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
    2. 3.2  Power Management
      1. 3.2.1 Internal 1.2-V Switching Regulator (DC-DC)
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1 Reset Sources
      2. 3.4.2 External Reset (XRS)
      3. 3.4.3 Power-On Reset (POR)
      4. 3.4.4 Debugger Reset (SYSRS)
      5. 3.4.5 Watchdog Reset (WDRS)
      6. 3.4.6 NMI Watchdog Reset (NMIWDRS)
      7. 3.4.7 DCSM Safe Code Copy Reset (SCCRESET)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
        1. 3.5.5.1 PIE Interrupt Priority
          1. 3.5.5.1.1 Channel Priority
          2. 3.5.5.1.2 Group Priority
      6. 3.5.6 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection
        2. 3.6.3.2 RAM Uncorrectable ECC Error
        3. 3.6.3.3 Flash Uncorrectable ECC Error
        4. 3.6.3.4 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 Error Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CAN Bit Clock
        6. 3.7.3.6 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 Clock Configuration Examples
      12. 3.7.12 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 IDLE
      2. 3.10.2 Guidelines on Software Emulation of STANDBY Mode
      3. 3.10.3 HALT
      4. 3.10.4 Flash Power-down Considerations
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1 Dedicated RAM (Mx RAM)
        2. 3.11.1.2 Local Shared RAM (LSx RAM)
        3. 3.11.1.3 Global Shared RAM (GSx RAM)
        4. 3.11.1.4 Message RAM (CLA MSGRAM)
        5. 3.11.1.5 Access Arbitration
        6. 3.11.1.6 Access Protection
          1. 3.11.1.6.1 CPU Fetch Protection
          2. 3.11.1.6.2 CPU Write Protection
          3. 3.11.1.6.3 CPU Read Protection
          4. 3.11.1.6.4 CLA Fetch Protection
          5. 3.11.1.6.5 CLA Write Protection
          6. 3.11.1.6.6 CLA Read Protection
          7. 3.11.1.6.7 DMA Write Protection
        7. 3.11.1.7 Memory Error Detection, Correction and Error Handling
          1. 3.11.1.7.1 Error Detection and Correction
          2. 3.11.1.7.2 Error Handling
        8. 3.11.1.8 Application Test Hooks for Error Detection and Correction
        9. 3.11.1.9 RAM Initialization
    12. 3.12 Flash and OTP Memory
      1. 3.12.1  Features
      2. 3.12.2  Flash Tools
      3. 3.12.3  Default Flash Configuration
      4. 3.12.4  Flash Bank, OTP and Pump
      5. 3.12.5  Flash Module Controller (FMC)
      6. 3.12.6  Flash and OTP and Wakeup Power-Down Modes
        1. 3.12.6.1 Flash/OTP and Pump Power Modes and Wakeup
        2. 3.12.6.2 Active Grace Period
      7. 3.12.7  Flash and OTP Performance
      8. 3.12.8  Flash Access Interface
        1. 3.12.8.1 Standard Access Mode
        2. 3.12.8.2 Prefetch Mode
        3. 3.12.8.3 Data Cache
      9. 3.12.9  Erase/Program Flash
        1. 3.12.9.1 Erase
        2. 3.12.9.2 Program
        3. 3.12.9.3 Verify
      10. 3.12.10 Error Correction Code (ECC) Protection
        1. 3.12.10.1 Single-Bit Data Error
        2. 3.12.10.2 Uncorrectable Error
        3. 3.12.10.3 SECDED Logic Correctness Check
        4. 3.12.10.4 Reading ECC Memory From a Higher Address Space
      11. 3.12.11 Reserved Locations Within Flash and OTP
      12. 3.12.12 Procedure to Change the Flash Control Registers
      13. 3.12.13 Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration
    13. 3.13 Dual Code Security Module (DCSM)
      1. 3.13.1 Functional Description
        1. 3.13.1.1 CSM Passwords
        2. 3.13.1.2 Emulation Code Security Logic (ECSL)
        3. 3.13.1.3 CPU Secure Logic
        4. 3.13.1.4 Execute-Only Protection
        5. 3.13.1.5 Password Lock
        6. 3.13.1.6 JTAG Lock
        7. 3.13.1.7 Link Pointer and Zone Select
      2. 3.13.2 C Code Example to Get Zone Select Block Addr for Zone1 in BANK0
      3. 3.13.3 Flash and OTP Erase/Program
      4. 3.13.4 Safe Copy Code
      5. 3.13.5 SafeCRC
      6. 3.13.6 CSM Impact on Other On-Chip Resources
      7. 3.13.7 Incorporating Code Security in User Applications
        1. 3.13.7.1 Environments That Require Security Unlocking
        2. 3.13.7.2 CSM Password Match Flow
        3. 3.13.7.3 C Code Example to Unsecure C28x Zone1
        4. 3.13.7.4 C Code Example to Resecure C28x Zone1
        5. 3.13.7.5 Environments That Require ECSL Unlocking
        6. 3.13.7.6 ECSL Password Match Flow
        7. 3.13.7.7 ECSL Disable Considerations for any Zone
          1. 3.13.7.7.1 C Code Example to Disable ECSL for C28x-Zone1
        8. 3.13.7.8 Device Unique ID
    14. 3.14 System Control Register Configuration Restrictions
    15. 3.15 System Control Registers
      1. 3.15.1  System Control Base Address Table
      2. 3.15.2  CPUTIMER_REGS Registers
      3. 3.15.3  PIE_CTRL_REGS Registers
      4. 3.15.4  WD_REGS Registers
      5. 3.15.5  NMI_INTRUPT_REGS Registers
      6. 3.15.6  XINT_REGS Registers
      7. 3.15.7  DMA_CLA_SRC_SEL_REGS Registers
      8. 3.15.8  DEV_CFG_REGS Registers
      9. 3.15.9  CLK_CFG_REGS Registers
      10. 3.15.10 CPU_SYS_REGS Registers
      11. 3.15.11 PERIPH_AC_REGS Registers
      12. 3.15.12 DCSM_BANK0_Z1_REGS Registers
      13. 3.15.13 DCSM_BANK0_Z2_REGS Registers
      14. 3.15.14 DCSM_COMMON_REGS Registers
      15. 3.15.15 DCSM_BANK1_Z1_REGS Registers
      16. 3.15.16 DCSM_BANK1_Z2_REGS Registers
      17. 3.15.17 MEM_CFG_REGS Registers
      18. 3.15.18 ACCESS_PROTECTION_REGS Registers
      19. 3.15.19 MEMORY_ERROR_REGS Registers
      20. 3.15.20 FLASH_CTRL_REGS Registers
      21. 3.15.21 FLASH_ECC_REGS Registers
      22. 3.15.22 UID_REGS Registers
      23. 3.15.23 DCSM_BANK0_Z1_OTP Registers
      24. 3.15.24 DCSM_BANK0_Z2_OTP Registers
      25. 3.15.25 DCSM_BANK1_Z1_OTP Registers
      26. 3.15.26 DCSM_BANK1_Z2_OTP Registers
      27. 3.15.27 Register to Driverlib Function Mapping
        1. 3.15.27.1 ASYSCTL Registers to Driverlib Functions
        2. 3.15.27.2 CPUTIMER Registers to Driverlib Functions
        3. 3.15.27.3 DCSM Registers to Driverlib Functions
        4. 3.15.27.4 FLASH Registers to Driverlib Functions
        5. 3.15.27.5 MEMCFG Registers to Driverlib Functions
        6. 3.15.27.6 NMI Registers to Driverlib Functions
        7. 3.15.27.7 PIE Registers to Driverlib Functions
        8. 3.15.27.8 SYSCTL Registers to Driverlib Functions
        9. 3.15.27.9 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Configuring Alternate Boot Mode Pins
      2. 4.3.2 Configuring Alternate Boot Mode Options
      3. 4.3.3 Boot Mode Example Use Cases
        1. 4.3.3.1 Zero Boot Mode Select Pins
        2. 4.3.3.2 One Boot Mode Select Pin
    4. 4.4 Device Boot Flow Diagrams
      1. 4.4.1 Emulation Boot Flow Diagram
      2. 4.4.2 Standalone Boot Flow Diagram
    5. 4.5 Device Reset and Exception Handling
      1. 4.5.1 Reset Causes and Handling
      2. 4.5.2 Exceptions and Interrupts Handling
    6. 4.6 Boot ROM Description
      1. 4.6.1  Boot ROM Registers
      2. 4.6.2  Boot ROM User OTP
      3. 4.6.3  Entry Points
      4. 4.6.4  Wait Points
      5. 4.6.5  Memory Maps
        1. 4.6.5.1 Boot ROM Memory Map
        2. 4.6.5.2 CLA Data ROM Memory Map
        3. 4.6.5.3 Reserved RAM and Flash Memory Map
      6. 4.6.6  ROM Tables
        1. 4.6.6.1 Boot ROM Tables
        2. 4.6.6.2 CLA ROM Tables
      7. 4.6.7  Boot Modes
        1. 4.6.7.1 Wait Boot Mode
        2. 4.6.7.2 SCI Boot Mode
        3. 4.6.7.3 SPI Boot Mode
        4. 4.6.7.4 I2C Boot Mode
        5. 4.6.7.5 Parallel Boot Mode
        6. 4.6.7.6 CAN Boot Mode
      8. 4.6.8  Boot Data Stream Structure
        1. 4.6.8.1 Bootloader Data Stream Structure
          1. 4.6.8.1.1 Data Stream Structure 8-bit
        2.       247
      9. 4.6.9  GPIO Assignments
      10. 4.6.10 Secure ROM Function APIs
      11. 4.6.11 DCSM Usage
      12. 4.6.12 Clock Initialization
      13. 4.6.13 Boot Status Information
        1. 4.6.13.1 Booting Status
        2. 4.6.13.2 Flash Single-Bit Error Status
      14. 4.6.14 ROM Version
    7. 4.7 The C2000 Hex Utility
      1. 4.7.1 HEX2000.exe Command Syntax
  7. 5 Control Law Accelerator (CLA)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 CLA Related Collateral
      3. 5.1.3 Block Diagram
    2. 5.2 CLA Interface
      1. 5.2.1 CLA Memory
      2. 5.2.2 CLA Memory Bus
      3. 5.2.3 Shared Peripherals and EALLOW Protection
      4. 5.2.4 CLA Tasks and Interrupt Vectors
      5. 5.2.5 CLA Software Interrupt to CPU
    3. 5.3 CLA, DMA, and CPU Arbitration
      1. 5.3.1 CLA Message RAM
      2. 5.3.2 CLA Program Memory
      3. 5.3.3 CLA Data Memory
      4. 5.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 5.4 CLA Configuration and Debug
      1. 5.4.1 Building a CLA Application
      2. 5.4.2 Typical CLA Initialization Sequence
      3. 5.4.3 Debugging CLA Code
        1. 5.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 5.4.3.2 Legacy Breakpoint Support (MDEBUGSTOP)
      4. 5.4.4 CLA Illegal Opcode Behavior
      5. 5.4.5 Resetting the CLA
    5. 5.5 Pipeline
      1. 5.5.1 Pipeline Overview
      2. 5.5.2 CLA Pipeline Alignment
        1. 5.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       286
        3. 5.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       288
        5. 5.5.2.3 ADC Early Interrupt to CLA Response
      3. 5.5.3 Parallel Instructions
        1. 5.5.3.1 Math Operation with Parallel Load
        2. 5.5.3.2 Multiply with Parallel Add
      4. 5.5.4 CLA Task Execution Latency
    6. 5.6 Software
      1. 5.6.1 CLA Examples
        1. 5.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 5.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        3. 5.6.1.3 CLA background nesting task
        4. 5.6.1.4 Controlling PWM output using CLA
        5. 5.6.1.5 Just-in-time ADC sampling with CLA
        6. 5.6.1.6 Optimal offloading of control algorithms to CLA
        7. 5.6.1.7 Handling shared resources across C28x and CLA
    7. 5.7 Instruction Set
      1. 5.7.1 Instruction Descriptions
      2. 5.7.2 Addressing Modes and Encoding
      3. 5.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCLRC BGINTM
        13.       MCMP32 MRa, MRb
        14.       MCMPF32 MRa, MRb
        15.       MCMPF32 MRa, #16FHi
        16.       MDEBUGSTOP
        17.       MDEBUGSTOP1
        18.       MEALLOW
        19.       MEDIS
        20.       MEINVF32 MRa, MRb
        21.       MEISQRTF32 MRa, MRb
        22.       MF32TOI16 MRa, MRb
        23.       MF32TOI16R MRa, MRb
        24.       MF32TOI32 MRa, MRb
        25.       MF32TOUI16 MRa, MRb
        26.       MF32TOUI16R MRa, MRb
        27.       MF32TOUI32 MRa, MRb
        28.       MFRACF32 MRa, MRb
        29.       MI16TOF32 MRa, MRb
        30.       MI16TOF32 MRa, mem16
        31.       MI32TOF32 MRa, mem32
        32.       MI32TOF32 MRa, MRb
        33.       MLSL32 MRa, #SHIFT
        34.       MLSR32 MRa, #SHIFT
        35.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        36.       MMAXF32 MRa, MRb
        37.       MMAXF32 MRa, #16FHi
        38.       MMINF32 MRa, MRb
        39.       MMINF32 MRa, #16FHi
        40.       MMOV16 MARx, MRa, #16I
        41.       MMOV16 MARx, mem16
        42.       MMOV16 mem16, MARx
        43.       MMOV16 mem16, MRa
        44.       MMOV32 mem32, MRa
        45.       MMOV32 mem32, MSTF
        46.       MMOV32 MRa, mem32 [, CNDF]
        47.       MMOV32 MRa, MRb [, CNDF]
        48.       MMOV32 MSTF, mem32
        49.       MMOVD32 MRa, mem32
        50.       MMOVF32 MRa, #32F
        51.       MMOVI16 MARx, #16I
        52.       MMOVI32 MRa, #32FHex
        53.       MMOVIZ MRa, #16FHi
        54.       MMOVZ16 MRa, mem16
        55.       MMOVXI MRa, #16FLoHex
        56.       MMPYF32 MRa, MRb, MRc
        57.       MMPYF32 MRa, #16FHi, MRb
        58.       MMPYF32 MRa, MRb, #16FHi
        59.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        60.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        61.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        62.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        63.       MNEGF32 MRa, MRb[, CNDF]
        64.       MNOP
        65.       MOR32 MRa, MRb, MRc
        66.       MRCNDD [CNDF]
        67.       MSETC BGINTM
        68.       MSETFLG FLAG, VALUE
        69.       MSTOP
        70.       MSUB32 MRa, MRb, MRc
        71.       MSUBF32 MRa, MRb, MRc
        72.       MSUBF32 MRa, #16FHi, MRb
        73.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        74.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        75.       MSWAPF MRa, MRb [, CNDF]
        76.       MTESTTF CNDF
        77.       MUI16TOF32 MRa, mem16
        78.       MUI16TOF32 MRa, MRb
        79.       MUI32TOF32 MRa, mem32
        80.       MUI32TOF32 MRa, MRb
        81.       MXOR32 MRa, MRb, MRc
    8. 5.8 CLA Registers
      1. 5.8.1 CLA Base Address Table
      2. 5.8.2 CLA_ONLY_REGS Registers
      3. 5.8.3 CLA_SOFTINT_REGS Registers
      4. 5.8.4 CLA_REGS Registers
      5. 5.8.5 CLA Registers to Driverlib Functions
  8. 6 Dual-Clock Comparator (DCC)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Block Diagram
    2. 6.2 Module Operation
      1. 6.2.1 Configuring DCC Counters
      2. 6.2.2 Single-Shot Measurement Mode
    3. 6.3 Interrupts
    4. 6.4 Software
      1. 6.4.1 DCC Examples
        1. 6.4.1.1 DCC Single shot Clock verification
        2. 6.4.1.2 DCC Single shot Clock measurement
        3. 6.4.1.3 DCC Continuous clock monitoring
        4. 6.4.1.4 DCC Continuous clock monitoring
        5. 6.4.1.5 DCC Detection of clock failure
    5. 6.5 DCC Registers
      1. 6.5.1 DCC Base Address Table
      2. 6.5.2 DCC_REGS Registers
      3. 6.5.3 DCC Registers to Driverlib Functions
  9. 7 CLA Program ROM CRC (CLAPROMCRC)
    1. 7.1 Overview
    2. 7.2 Functional Description
      1. 7.2.1 Start Address
      2. 7.2.2 Seed
      3. 7.2.3 Halt
      4. 7.2.4 Result and Comparison
    3. 7.3 Software
      1. 7.3.1 CLAPROMCRC Examples
        1. 7.3.1.1 CLAPROMCRC CPU Interrupt Example
    4. 7.4 CLAPROM Registers
      1. 7.4.1 CLA PROM CRC Base Address Table
      2. 7.4.2 CLA_PROM_CRC32_REGS Registers
      3. 7.4.3 CLAPROMCRC Registers to Driverlib Functions
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1 Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2 Configuration Overview
    3. 8.3 Digital Inputs on ADC Pins (AIOs)
    4. 8.4 Digital General-Purpose I/O Control
    5. 8.5 Input Qualification
      1. 8.5.1 No Synchronization (Asynchronous Input)
      2. 8.5.2 Synchronization to SYSCLKOUT Only
      3. 8.5.3 Qualification Using a Sampling Window
    6. 8.6 GPIO and Peripheral Muxing
      1. 8.6.1 GPIO Muxing
      2. 8.6.2 Peripheral Muxing
    7. 8.7 Internal Pullup Configuration Requirements
    8. 8.8 Software
      1. 8.8.1 GPIO Examples
        1. 8.8.1.1 Device GPIO Setup
        2. 8.8.1.2 Device GPIO Toggle
        3. 8.8.1.3 Device GPIO Interrupt
        4. 8.8.1.4 External Interrupt (XINT)
      2. 8.8.2 LED Examples
        1. 8.8.2.1 LED Blinky Example with DCSM
    9. 8.9 GPIO Registers
      1. 8.9.1 GPIO Base Address Table
      2. 8.9.2 GPIO_CTRL_REGS Registers
      3. 8.9.3 GPIO_DATA_REGS Registers
      4. 8.9.4 GPIO Registers to Driverlib Functions
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 ePWM, CLB, and GPIO Output X-BAR
      1. 9.2.1 ePWM X-BAR
        1. 9.2.1.1 ePWM X-BAR Architecture
      2. 9.2.2 CLB X-BAR
        1. 9.2.2.1 CLB X-BAR Architecture
      3. 9.2.3 GPIO Output X-BAR
        1. 9.2.3.1 GPIO Output X-BAR Architecture
      4. 9.2.4 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 EPWM_XBAR_REGS Registers
      5. 9.3.5 CLB_XBAR_REGS Registers
      6. 9.3.6 OUTPUT_XBAR_REGS Registers
      7. 9.3.7 Register to Driverlib Function Mapping
        1. 9.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 9.3.7.2 XBAR Registers to Driverlib Functions
        3. 9.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 9.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 9.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 CPU and CLA Arbitration
    6. 10.6 Channel Priority
      1. 10.6.1 Round-Robin Mode
      2. 10.6.2 Channel 1 High-Priority Mode
    7. 10.7 Overrun Detection Feature
    8. 10.8 Software
      1. 10.8.1 DMA Examples
        1. 10.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.8.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 10.9 DMA Registers
      1. 10.9.1 DMA Base Address Table
      2. 10.9.2 DMA_REGS Registers
      3. 10.9.3 DMA_CH_REGS Registers
      4. 10.9.4 DMA_CLA_SRC_SEL_REGS Registers
      5. 10.9.5 DMA Registers to Driverlib Functions
  13. 11Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 11.1 Introduction
      1. 11.1.1 ERAD Related Collateral
    2. 11.2 Enhanced Bus Comparator Unit
      1. 11.2.1 Enhanced Bus Comparator Unit Operations
    3. 11.3 System Event Counter Unit
      1. 11.3.1 System Event Counter Modes
        1. 11.3.1.1 Counting Active Levels Versus Edges
        2. 11.3.1.2 Max Mode
        3. 11.3.1.3 Input Signal Selection
      2. 11.3.2 Reset on Event
      3. 11.3.3 Operation Conditions
    4. 11.4 ERAD Ownership, Initialization and Reset
    5. 11.5 ERAD Programming Sequence
      1. 11.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 11.5.2 Timer and Counter Programming Sequence
    6. 11.6 Software
      1. 11.6.1 ERAD Examples
        1. 11.6.1.1  ERAD Profiling Interrupts
        2. 11.6.1.2  ERAD Profile Function
        3. 11.6.1.3  ERAD Profile Function
        4. 11.6.1.4  ERAD HWBP Monitor Program Counter
        5. 11.6.1.5  ERAD HWBP Monitor Program Counter
        6. 11.6.1.6  ERAD Profile Function
        7. 11.6.1.7  ERAD HWBP Stack Overflow Detection
        8. 11.6.1.8  ERAD HWBP Stack Overflow Detection
        9. 11.6.1.9  ERAD Stack Overflow
        10. 11.6.1.10 ERAD Profile Interrupts CLA
        11. 11.6.1.11 ERAD Profiling Interrupts
        12. 11.6.1.12 ERAD Profiling Interrupts
        13. 11.6.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 11.6.1.14 ERAD INTERRUPT ORDER
        15. 11.6.1.15 ERAD AND CLB
        16. 11.6.1.16 ERAD PWM PROTECTION
    7. 11.7 ERAD Registers
      1. 11.7.1 ERAD Base Address Table
      2. 11.7.2 ERAD_GLOBAL_REGS Registers
      3. 11.7.3 ERAD_HWBP_REGS Registers
      4. 11.7.4 ERAD_COUNTER_REGS Registers
      5. 11.7.5 ERAD Registers to Driverlib Functions
  14. 12Analog Subsystem
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Optimizing Power-Up Time
    3. 12.3 Digital Inputs on ADC Pins (AIOs)
    4. 12.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 12.5 Analog Pins and Internal Connections
    6. 12.6 Analog Subsystem Registers
      1. 12.6.1 Analog Subsystem Base Address Table
      2. 12.6.2 ANALOG_SUBSYS_REGS Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1  Introduction
      1. 13.1.1 ADC Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Block Diagram
    2. 13.2  ADC Configurability
      1. 13.2.1 Clock Configuration
      2. 13.2.2 Resolution
      3. 13.2.3 Voltage Reference
        1. 13.2.3.1 External Reference Mode
        2. 13.2.3.2 Internal Reference Mode
        3. 13.2.3.3 Ganged References
        4. 13.2.3.4 Selecting Reference Mode
      4. 13.2.4 Signal Mode
      5. 13.2.5 Expected Conversion Results
      6. 13.2.6 Interpreting Conversion Results
    3. 13.3  SOC Principle of Operation
      1. 13.3.1 SOC Configuration
      2. 13.3.2 Trigger Operation
      3. 13.3.3 ADC Acquisition (Sample and Hold) Window
      4. 13.3.4 ADC Input Models
      5. 13.3.5 Channel Selection
    4. 13.4  SOC Configuration Examples
      1. 13.4.1 Single Conversion from ePWM Trigger
      2. 13.4.2 Oversampled Conversion from ePWM Trigger
      3. 13.4.3 Multiple Conversions from CPU Timer Trigger
      4. 13.4.4 Software Triggering of SOCs
    5. 13.5  ADC Conversion Priority
    6. 13.6  Burst Mode
      1. 13.6.1 Burst Mode Example
      2. 13.6.2 Burst Mode Priority Example
    7. 13.7  EOC and Interrupt Operation
      1. 13.7.1 Interrupt Overflow
      2. 13.7.2 Continue to Interrupt Mode
      3. 13.7.3 Early Interrupt Configuration Mode
    8. 13.8  Post-Processing Blocks
      1. 13.8.1 PPB Offset Correction
      2. 13.8.2 PPB Error Calculation
      3. 13.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 13.8.4 PPB Sample Delay Capture
    9. 13.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 13.9.1 Implementation
      2. 13.9.2 Detecting an Open Input Pin
      3. 13.9.3 Detecting a Shorted Input Pin
    10. 13.10 Power-Up Sequence
    11. 13.11 ADC Calibration
      1. 13.11.1 ADC Zero Offset Calibration
    12. 13.12 ADC Timings
      1. 13.12.1 ADC Timing Diagrams
    13. 13.13 Additional Information
      1. 13.13.1 Ensuring Synchronous Operation
        1. 13.13.1.1 Basic Synchronous Operation
        2. 13.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 13.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 13.13.1.4 Non-overlapping Conversions
      2. 13.13.2 Choosing an Acquisition Window Duration
      3. 13.13.3 Achieving Simultaneous Sampling
      4. 13.13.4 Result Register Mapping
      5. 13.13.5 Internal Temperature Sensor
      6. 13.13.6 Designing an External Reference Circuit
      7. 13.13.7 ADC-DAC Loopback Testing
      8. 13.13.8 Internal Test Mode
      9. 13.13.9 ADC Gain and Offset Calibration
    14. 13.14 Software
      1. 13.14.1 ADC Examples
        1. 13.14.1.1  ADC Software Triggering
        2. 13.14.1.2  ADC ePWM Triggering
        3. 13.14.1.3  ADC Temperature Sensor Conversion
        4. 13.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 13.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 13.14.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        7. 13.14.1.7  ADC PPB Offset (adc_ppb_offset)
        8. 13.14.1.8  ADC PPB Limits (adc_ppb_limits)
        9. 13.14.1.9  ADC PPB Delay Capture (adc_ppb_delay)
        10. 13.14.1.10 ADC ePWM Triggering Multiple SOC
        11. 13.14.1.11 ADC Burst Mode
        12. 13.14.1.12 ADC Burst Mode Oversampling
        13. 13.14.1.13 ADC SOC Oversampling
        14. 13.14.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip)
        15. 13.14.1.15 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 13.15 ADC Registers
      1. 13.15.1 ADC Base Address Table
      2. 13.15.2 ADC_RESULT_REGS Registers
      3. 13.15.3 ADC_REGS Registers
      4. 13.15.4 ADC Registers to Driverlib Functions
  16. 14Programmable Gain Amplifier (PGA)
    1. 14.1  Programmable Gain Amplifier (PGA) Overview
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
    2. 14.2  Linear Output Range
    3. 14.3  Gain Modes
    4. 14.4  External Filtering
    5. 14.5  Error Calibration
      1. 14.5.1 Offset Error
      2. 14.5.2 Gain Error
    6. 14.6  Ground Routing
    7. 14.7  Enabling and Disabling the PGA Clock
    8. 14.8  Lock Register
    9. 14.9  Examples
      1. 14.9.1 Direct Amplifier
      2. 14.9.2 RC Filter
    10. 14.10 Analog Front End Integration
      1. 14.10.1 ADC
        1. 14.10.1.1 Unfiltered Acquisition Window
        2. 14.10.1.2 Filtered Acquisition Window
      2. 14.10.2 CMPSS
      3. 14.10.3 Buffered DAC
      4. 14.10.4 Alternate Functions
    11. 14.11 Software
      1. 14.11.1 PGA Examples
        1. 14.11.1.1 PGA DAC-ADC External Loopback Example
        2. 14.11.1.2 PGA DAC-ADC External Loopback Example
    12. 14.12 PGA Registers
      1. 14.12.1 PGA Base Address Table
      2. 14.12.2 PGA_REGS Registers
      3. 14.12.3 PGA Registers to Driverlib Functions
  17. 15Buffered Digital-to-Analog Converter (DAC)
    1. 15.1 Introduction
      1. 15.1.1 DAC Related Collateral
      2. 15.1.2 Features
      3. 15.1.3 Block Diagram
    2. 15.2 Using the DAC
      1. 15.2.1 Initialization Sequence
      2. 15.2.2 DAC Offset Adjustment
      3. 15.2.3 EPWMSYNCPER Signal
    3. 15.3 Lock Registers
    4. 15.4 Software
      1. 15.4.1 DAC Examples
        1. 15.4.1.1 Buffered DAC Enable
        2. 15.4.1.2 Buffered DAC Random
        3. 15.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 15.5 DAC Registers
      1. 15.5.1 DAC Base Address Table
      2. 15.5.2 DAC_REGS Registers
      3. 15.5.3 DAC Registers to Driverlib Functions
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 CMPSS Related Collateral
      2. 16.1.2 Features
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Ramp Generator
      1. 16.4.1 Ramp Generator Overview
      2. 16.4.2 Ramp Generator Behavior
      3. 16.4.3 Ramp Generator Behavior at Corner Cases
    5. 16.5 Digital Filter
      1. 16.5.1 Filter Initialization Sequence
    6. 16.6 Using the CMPSS
      1. 16.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 16.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.6.3 Calibrating the CMPSS
      4. 16.6.4 Enabling and Disabling the CMPSS Clock
    7. 16.7 Software
      1. 16.7.1 CMPSS Examples
        1. 16.7.1.1 CMPSS Asynchronous Trip
        2. 16.7.1.2 CMPSS Digital Filter Configuration
    8. 16.8 CMPSS Registers
      1. 16.8.1 CMPSS Base Address Table
      2. 16.8.2 CMPSS_REGS Registers
      3. 16.8.3 CMPSS Registers to Driverlib Functions
  19. 17Sigma Delta Filter Module (SDFM)
    1. 17.1  Introduction
      1. 17.1.1 SDFM Related Collateral
      2. 17.1.2 Features
      3. 17.1.3 Block Diagram
    2. 17.2  Configuring Device Pins
    3. 17.3  Input Control Unit
    4. 17.4  Sinc Filter
      1. 17.4.1 Data Rate and Latency of the Sinc Filter
    5. 17.5  Data (Primary) Filter Unit
      1. 17.5.1 32-bit or 16-bit Data Filter Output Representation
      2. 17.5.2 Data FIFO
      3. 17.5.3 SDSYNC Event
    6. 17.6  Comparator (Secondary) Filter Unit
      1. 17.6.1 Higher Threshold (HLT) Comparators
      2. 17.6.2 Lower Threshold (LLT) Comparators
    7. 17.7  Theoretical SDFM Filter Output
    8. 17.8  Interrupt Unit
      1. 17.8.1 SDFM (SDyERR) Interrupt Sources
      2. 17.8.2 Data Ready (DRINT) Interrupt Sources
    9. 17.9  Software
      1. 17.9.1 SDFM Examples
        1. 17.9.1.1 SDFM Filter Sync CPU
        2. 17.9.1.2 SDFM Filter Sync CLA
        3. 17.9.1.3 SDFM Filter Sync DMA
        4. 17.9.1.4 SDFM PWM Sync
        5. 17.9.1.5 SDFM Type 1 Filter FIFO
    10. 17.10 SDFM Registers
      1. 17.10.1 SDFM Base Address Table
      2. 17.10.2 SDFM_REGS Registers
      3. 17.10.3 SDFM Registers to Driverlib Functions
  20. 18Enhanced Pulse Width Modulator (ePWM)
    1. 18.1  Introduction
      1. 18.1.1 EPWM Related Collateral
      2. 18.1.2 Submodule Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  ePWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 18.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 18.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 18.4.7 Global Load
        1. 18.4.7.1 Global Load Pulse Pre-Scalar
        2. 18.4.7.2 One-Shot Load Mode
        3. 18.4.7.3 One-Shot Sync Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  PWM Chopper (PC) Submodule
      1. 18.8.1 Purpose of the PWM Chopper Submodule
      2. 18.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 18.8.3 Waveforms
        1. 18.8.3.1 One-Shot Pulse
        2. 18.8.3.2 Duty Cycle Control
    9. 18.9  Trip-Zone (TZ) Submodule
      1. 18.9.1 Purpose of the Trip-Zone Submodule
      2. 18.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.9.2.1 Trip-Zone Configurations
      3. 18.9.3 Generating Trip Event Interrupts
    10. 18.10 Event-Trigger (ET) Submodule
      1. 18.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 18.11 Digital Compare (DC) Submodule
      1. 18.11.1 Purpose of the Digital Compare Submodule
      2. 18.11.2 Enhanced Trip Action Using CMPSS
      3. 18.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 18.11.4 Operation Highlights of the Digital Compare Submodule
        1. 18.11.4.1 Digital Compare Events
        2. 18.11.4.2 Event Filtering
        3. 18.11.4.3 Valley Switching
    12. 18.12 ePWM Crossbar (X-BAR)
    13. 18.13 Applications to Power Topologies
      1. 18.13.1  Overview of Multiple Modules
      2. 18.13.2  Key Configuration Capabilities
      3. 18.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 18.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 18.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 18.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 18.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 18.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 18.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 18.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 18.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 18.14 Register Lock Protection
    15. 18.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 18.15.1 Operational Description of HRPWM
        1. 18.15.1.1 Controlling the HRPWM Capabilities
        2. 18.15.1.2 HRPWM Source Clock
        3. 18.15.1.3 Configuring the HRPWM
        4. 18.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 18.15.1.5 Principle of Operation
          1. 18.15.1.5.1 Edge Positioning
          2. 18.15.1.5.2 Scaling Considerations
          3. 18.15.1.5.3 Duty Cycle Range Limitation
          4. 18.15.1.5.4 High-Resolution Period
            1. 18.15.1.5.4.1 High-Resolution Period Configuration
        6. 18.15.1.6 Deadband High-Resolution Operation
        7. 18.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 18.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 18.15.1.8.1 #Defines for HRPWM Header Files
          2. 18.15.1.8.2 Implementing a Simple Buck Converter
            1. 18.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 18.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 18.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 18.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 18.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 18.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 18.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 18.15.2.2 Software Usage
          1. 18.15.2.2.1 A Sample of How to Add "Include" Files
          2.        840
          3. 18.15.2.2.2 Declaring an Element
          4.        842
          5. 18.15.2.2.3 Initializing With a Scale Factor Value
          6.        844
          7. 18.15.2.2.4 SFO Function Calls
    16. 18.16 Software
      1. 18.16.1 EPWM Examples
        1. 18.16.1.1  ePWM Trip Zone
        2. 18.16.1.2  ePWM Up Down Count Action Qualifier
        3. 18.16.1.3  ePWM Synchronization
        4. 18.16.1.4  ePWM Digital Compare
        5. 18.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 18.16.1.6  ePWM Valley Switching
        7. 18.16.1.7  ePWM Digital Compare Edge Filter
        8. 18.16.1.8  ePWM Deadband
        9. 18.16.1.9  ePWM DMA
        10. 18.16.1.10 ePWM Chopper
        11. 18.16.1.11 EPWM Configure Signal
        12. 18.16.1.12 Realization of Monoshot mode
        13. 18.16.1.13 EPWM Action Qualifier (epwm_up_aq)
      2. 18.16.2 HRPWM Examples
        1. 18.16.2.1 HRPWM Duty Control with SFO
        2. 18.16.2.2 HRPWM Slider
        3. 18.16.2.3 HRPWM Period Control
        4. 18.16.2.4 HRPWM Duty Control with UPDOWN Mode
    17. 18.17 ePWM Registers
      1. 18.17.1 ePWM Base Address Table
      2. 18.17.2 EPWM_REGS Registers
      3. 18.17.3 SYNC_SOC_REGS Registers
      4. 18.17.4 Register to Driverlib Function Mapping
        1. 18.17.4.1 EPWM Registers to Driverlib Functions
        2. 18.17.4.2 HRPWM Registers to Driverlib Functions
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1  Event Prescaler
      2. 19.5.2  Edge Polarity Select and Qualifier
      3. 19.5.3  Continuous/One-Shot Control
      4. 19.5.4  32-Bit Counter and Phase Control
      5. 19.5.5  CAP1-CAP4 Registers
      6. 19.5.6  eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7  Interrupt Control
      8. 19.5.8  DMA Interrupt
      9. 19.5.9  Shadow Load and Lockout Control
      10. 19.5.10 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 Software
      1. 19.8.1 ECAP Examples
        1. 19.8.1.1 eCAP APWM Example
        2. 19.8.1.2 eCAP Capture PWM Example
        3. 19.8.1.3 eCAP APWM Phase-shift Example
        4. 19.8.1.4 eCAP Software Sync Example
    9. 19.9 eCAP Registers
      1. 19.9.1 eCAP Base Address Table
      2. 19.9.2 ECAP_REGS Registers
      3. 19.9.3 ECAP Registers to Driverlib Functions
  22. 20High Resolution Capture (HRCAP)
    1. 20.1 Introduction
      1. 20.1.1 HRCAP Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Description
    2. 20.2 Operational Details
      1. 20.2.1 HRCAP Clocking
      2. 20.2.2 HRCAP Initialization Sequence
      3. 20.2.3 HRCAP Interrupts
      4. 20.2.4 HRCAP Calibration
        1. 20.2.4.1 Applying the Scale Factor
    3. 20.3 Known Exceptions
    4. 20.4 Software
      1. 20.4.1 HRCAP Examples
        1. 20.4.1.1 HRCAP Capture and Calibration Example
    5. 20.5 HRCAP Registers
      1. 20.5.1 HRCAP Base Address Table
      2. 20.5.2 HRCAP_REGS Registers
      3. 20.5.3 HRCAP Registers to Driverlib Functions
  23. 21Enhanced Quadrature Encoder Pulse (eQEP)
    1. 21.1  Introduction
      1. 21.1.1 EQEP Related Collateral
    2. 21.2  Configuring Device Pins
    3. 21.3  Description
      1. 21.3.1 EQEP Inputs
      2. 21.3.2 Functional Description
      3. 21.3.3 eQEP Memory Map
    4. 21.4  Quadrature Decoder Unit (QDU)
      1. 21.4.1 Position Counter Input Modes
        1. 21.4.1.1 Quadrature Count Mode
        2. 21.4.1.2 Direction-Count Mode
        3. 21.4.1.3 Up-Count Mode
        4. 21.4.1.4 Down-Count Mode
      2. 21.4.2 eQEP Input Polarity Selection
      3. 21.4.3 Position-Compare Sync Output
    5. 21.5  Position Counter and Control Unit (PCCU)
      1. 21.5.1 Position Counter Operating Modes
        1. 21.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 21.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 21.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 21.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 21.5.2 Position Counter Latch
        1. 21.5.2.1 Index Event Latch
        2. 21.5.2.2 Strobe Event Latch
      3. 21.5.3 Position Counter Initialization
      4. 21.5.4 eQEP Position-compare Unit
    6. 21.6  eQEP Edge Capture Unit
    7. 21.7  eQEP Watchdog
    8. 21.8  eQEP Unit Timer Base
    9. 21.9  QMA Module
      1. 21.9.1 Modes of Operation
        1. 21.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 21.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 21.9.2 Interrupt and Error Generation
    10. 21.10 eQEP Interrupt Structure
    11. 21.11 eQEP Registers
      1. 21.11.1 eQEP Base Address Table
      2. 21.11.2 EQEP_REGS Registers
      3. 21.11.3 EQEP Registers to Driverlib Functions
  24. 22Serial Peripheral Interface (SPI)
    1. 22.1 Introduction
      1. 22.1.1 Features
      2. 22.1.2 SPI Related Collateral
      3. 22.1.3 Block Diagram
    2. 22.2 System-Level Integration
      1. 22.2.1 SPI Module Signals
      2. 22.2.2 Configuring Device Pins
        1. 22.2.2.1 GPIOs Required for High-Speed Mode
      3. 22.2.3 SPI Interrupts
      4. 22.2.4 DMA Support
    3. 22.3 SPI Operation
      1. 22.3.1  Introduction to Operation
      2. 22.3.2  Master Mode
      3. 22.3.3  Slave Mode
      4. 22.3.4  Data Format
        1. 22.3.4.1 Transmission of Bit from SPIRXBUF
      5. 22.3.5  Baud Rate Selection
        1. 22.3.5.1 Baud Rate Determination
        2. 22.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 22.3.6  SPI Clocking Schemes
      7. 22.3.7  SPI FIFO Description
      8. 22.3.8  SPI DMA Transfers
        1. 22.3.8.1 Transmitting Data Using SPI with DMA
        2. 22.3.8.2 Receiving Data Using SPI with DMA
      9. 22.3.9  SPI High-Speed Mode
      10. 22.3.10 SPI 3-Wire Mode Description
    4. 22.4 Programming Procedure
      1. 22.4.1 Initialization Upon Reset
      2. 22.4.2 Configuring the SPI
      3. 22.4.3 Configuring the SPI for High-Speed Mode
      4. 22.4.4 Data Transfer Example
      5. 22.4.5 SPI 3-Wire Mode Code Examples
        1. 22.4.5.1 3-Wire Master Mode Transmit
        2.       1002
          1. 22.4.5.2.1 3-Wire Master Mode Receive
        3.       1004
          1. 22.4.5.2.1 3-Wire Slave Mode Transmit
        4.       1006
          1. 22.4.5.2.1 3-Wire Slave Mode Receive
      6. 22.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 22.5 Software
      1. 22.5.1 SPI Examples
        1. 22.5.1.1 SPI Digital Loopback
        2. 22.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 22.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 22.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 22.5.1.5 SPI Digital Loopback with DMA
        6. 22.5.1.6 SPI EEPROM
        7. 22.5.1.7 SPI DMA EEPROM
    6. 22.6 SPI Registers
      1. 22.6.1 SPI Base Address Table
      2. 22.6.2 SPI_REGS Registers
      3. 22.6.3 SPI Registers to Driverlib Functions
  25. 23Serial Communications Interface (SCI)
    1. 23.1  Introduction
      1. 23.1.1 Features
      2. 23.1.2 SCI Related Collateral
      3. 23.1.3 Block Diagram
    2. 23.2  Architecture
    3. 23.3  SCI Module Signal Summary
    4. 23.4  Configuring Device Pins
    5. 23.5  Multiprocessor and Asynchronous Communication Modes
    6. 23.6  SCI Programmable Data Format
    7. 23.7  SCI Multiprocessor Communication
      1. 23.7.1 Recognizing the Address Byte
      2. 23.7.2 Controlling the SCI TX and RX Features
      3. 23.7.3 Receipt Sequence
    8. 23.8  Idle-Line Multiprocessor Mode
      1. 23.8.1 Idle-Line Mode Steps
      2. 23.8.2 Block Start Signal
      3. 23.8.3 Wake-Up Temporary (WUT) Flag
        1. 23.8.3.1 Sending a Block Start Signal
      4. 23.8.4 Receiver Operation
    9. 23.9  Address-Bit Multiprocessor Mode
      1. 23.9.1 Sending an Address
    10. 23.10 SCI Communication Format
      1. 23.10.1 Receiver Signals in Communication Modes
      2. 23.10.2 Transmitter Signals in Communication Modes
    11. 23.11 SCI Port Interrupts
      1. 23.11.1 Break Detect
    12. 23.12 SCI Baud Rate Calculations
    13. 23.13 SCI Enhanced Features
      1. 23.13.1 SCI FIFO Description
      2. 23.13.2 SCI Auto-Baud
      3. 23.13.3 Autobaud-Detect Sequence
    14. 23.14 Software
      1. 23.14.1 SCI Examples
        1. 23.14.1.1 Tune Baud Rate via UART Example
        2. 23.14.1.2 SCI FIFO Digital Loop Back
        3. 23.14.1.3 SCI Interrupt Echoback
        4. 23.14.1.4 SCI Interrupt Echoback with FIFO
        5. 23.14.1.5 SCI Echoback
    15. 23.15 SCI Registers
      1. 23.15.1 SCI Base Address Table
      2. 23.15.2 SCI_REGS Registers
      3. 23.15.3 SCI Registers to Driverlib Functions
  26. 24Inter-Integrated Circuit Module (I2C)
    1. 24.1 Introduction
      1. 24.1.1 I2C Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Features Not Supported
      4. 24.1.4 Functional Overview
      5. 24.1.5 Clock Generation
      6. 24.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 24.1.6.1 Formula for the Master Clock Period
    2. 24.2 Configuring Device Pins
    3. 24.3 I2C Module Operational Details
      1. 24.3.1  Input and Output Voltage Levels
      2. 24.3.2  Selecting Pullup Resistors
      3. 24.3.3  Data Validity
      4. 24.3.4  Operating Modes
      5. 24.3.5  I2C Module START and STOP Conditions
      6. 24.3.6  Non-repeat Mode versus Repeat Mode
      7. 24.3.7  Serial Data Formats
        1. 24.3.7.1 7-Bit Addressing Format
        2. 24.3.7.2 10-Bit Addressing Format
        3. 24.3.7.3 Free Data Format
        4. 24.3.7.4 Using a Repeated START Condition
      8. 24.3.8  Clock Synchronization
      9. 24.3.9  Arbitration
      10. 24.3.10 Digital Loopback Mode
      11. 24.3.11 NACK Bit Generation
    4. 24.4 Interrupt Requests Generated by the I2C Module
      1. 24.4.1 Basic I2C Interrupt Requests
      2. 24.4.2 I2C FIFO Interrupts
    5. 24.5 Resetting or Disabling the I2C Module
    6. 24.6 Software
      1. 24.6.1 I2C Examples
        1. 24.6.1.1 I2C Digital Loopback with FIFO Interrupts
        2. 24.6.1.2 I2C EEPROM
        3. 24.6.1.3 I2C EEPROM
        4. 24.6.1.4 I2C EEPROM
    7. 24.7 I2C Registers
      1. 24.7.1 I2C Base Address Table
      2. 24.7.2 I2C_REGS Registers
      3. 24.7.3 I2C Registers to Driverlib Functions
  27. 25Power Management Bus Module (PMBus)
    1. 25.1 Introduction
      1. 25.1.1 PMBUS Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Configuring Device Pins
    3. 25.3 Slave Mode Operation
      1. 25.3.1 Configuration
      2. 25.3.2 Message Handling
        1. 25.3.2.1  Quick Command
        2. 25.3.2.2  Send Byte
        3. 25.3.2.3  Receive Byte
        4. 25.3.2.4  Write Byte and Write Word
        5. 25.3.2.5  Read Byte and Read Word
        6. 25.3.2.6  Process Call
        7. 25.3.2.7  Block Write
        8. 25.3.2.8  Block Read
        9. 25.3.2.9  Block Write-Block Read Process Call
        10. 25.3.2.10 Alert Response
        11. 25.3.2.11 Extended Command
        12. 25.3.2.12 Group Command
    4. 25.4 Master Mode Operation
      1. 25.4.1 Configuration
      2. 25.4.2 Message Handling
        1. 25.4.2.1  Quick Command
        2. 25.4.2.2  Send Byte
        3. 25.4.2.3  Receive Byte
        4. 25.4.2.4  Write Byte and Write Word
        5. 25.4.2.5  Read Byte and Read Word
        6. 25.4.2.6  Process Call
        7. 25.4.2.7  Block Write
        8. 25.4.2.8  Block Read
        9. 25.4.2.9  Block Write-Block Read Process Call
        10. 25.4.2.10 Alert Response
        11. 25.4.2.11 Extended Command
        12. 25.4.2.12 Group Command
    5. 25.5 PMBus Registers
      1. 25.5.1 PMBus Base Address Table
      2. 25.5.2 PMBUS_REGS Registers
      3. 25.5.3 PMBUS Registers to Driverlib Functions
  28. 26Controller Area Network (CAN)
    1. 26.1  Introduction
      1. 26.1.1 DCAN Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
        1. 26.1.3.1 CAN Core
        2. 26.1.3.2 Message Handler
        3. 26.1.3.3 Message RAM
        4. 26.1.3.4 Registers and Message Object Access (IFx)
    2. 26.2  Functional Description
      1. 26.2.1 Configuring Device Pins
      2. 26.2.2 Address/Data Bus Bridge
    3. 26.3  Operating Modes
      1. 26.3.1 Initialization
      2. 26.3.2 CAN Message Transfer (Normal Operation)
        1. 26.3.2.1 Disabled Automatic Retransmission
        2. 26.3.2.2 Auto-Bus-On
      3. 26.3.3 Test Modes
        1. 26.3.3.1 Silent Mode
        2. 26.3.3.2 Loopback Mode
        3. 26.3.3.3 External Loopback Mode
        4. 26.3.3.4 Loopback Combined with Silent Mode
    4. 26.4  Multiple Clock Source
    5. 26.5  Interrupt Functionality
      1. 26.5.1 Message Object Interrupts
      2. 26.5.2 Status Change Interrupts
      3. 26.5.3 Error Interrupts
      4. 26.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 26.5.5 Interrupt Topologies
    6. 26.6  DMA Functionality
    7. 26.7  Parity Check Mechanism
      1. 26.7.1 Behavior on Parity Error
    8. 26.8  Debug Mode
    9. 26.9  Module Initialization
    10. 26.10 Configuration of Message Objects
      1. 26.10.1 Configuration of a Transmit Object for Data Frames
      2. 26.10.2 Configuration of a Transmit Object for Remote Frames
      3. 26.10.3 Configuration of a Single Receive Object for Data Frames
      4. 26.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 26.10.5 Configuration of a FIFO Buffer
    11. 26.11 Message Handling
      1. 26.11.1  Message Handler Overview
      2. 26.11.2  Receive/Transmit Priority
      3. 26.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 26.11.4  Updating a Transmit Object
      5. 26.11.5  Changing a Transmit Object
      6. 26.11.6  Acceptance Filtering of Received Messages
      7. 26.11.7  Reception of Data Frames
      8. 26.11.8  Reception of Remote Frames
      9. 26.11.9  Reading Received Messages
      10. 26.11.10 Requesting New Data for a Receive Object
      11. 26.11.11 Storing Received Messages in FIFO Buffers
      12. 26.11.12 Reading from a FIFO Buffer
    12. 26.12 CAN Bit Timing
      1. 26.12.1 Bit Time and Bit Rate
        1. 26.12.1.1 Synchronization Segment
        2. 26.12.1.2 Propagation Time Segment
        3. 26.12.1.3 Phase Buffer Segments and Synchronization
        4. 26.12.1.4 Oscillator Tolerance Range
      2. 26.12.2 Configuration of the CAN Bit Timing
        1. 26.12.2.1 Calculation of the Bit Timing Parameters
        2. 26.12.2.2 Example for Bit Timing at High Baudrate
        3. 26.12.2.3 Example for Bit Timing at Low Baudrate
    13. 26.13 Message Interface Register Sets
      1. 26.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 26.13.2 Message Interface Register Set 3 (IF3)
    14. 26.14 Message RAM
      1. 26.14.1 Structure of Message Objects
      2. 26.14.2 Addressing Message Objects in RAM
      3. 26.14.3 Message RAM Representation in Debug Mode
    15. 26.15 Software
      1. 26.15.1 CAN Examples
        1. 26.15.1.1 CAN External Loopback
        2. 26.15.1.2 CAN External Loopback with Interrupts
        3. 26.15.1.3 CAN-A to CAN-B External Transmit
        4. 26.15.1.4 CAN External Loopback with DMA
        5. 26.15.1.5 CAN Transmit and Receive Configurations
        6. 26.15.1.6 CAN Error Generation Example
        7. 26.15.1.7 CAN Remote Request Loopback
        8. 26.15.1.8 CAN example that illustrates the usage of Mask registers
    16. 26.16 CAN Registers
      1. 26.16.1 CAN Base Address Table
      2. 26.16.2 CAN_REGS Registers
      3. 26.16.3 CAN Registers to Driverlib Functions
  29. 27Local Interconnect Network (LIN)
    1. 27.1 Introduction
      1. 27.1.1 SCI Features
      2. 27.1.2 LIN Features
      3. 27.1.3 LIN Related Collateral
      4. 27.1.4 Block Diagram
    2. 27.2 Serial Communications Interface Module
      1. 27.2.1 SCI Communication Formats
        1. 27.2.1.1 SCI Frame Formats
        2. 27.2.1.2 SCI Asynchronous Timing Mode
        3. 27.2.1.3 SCI Baud Rate
          1. 27.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 27.2.1.4 SCI Multiprocessor Communication Modes
          1. 27.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 27.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 27.2.1.5 SCI Multibuffered Mode
      2. 27.2.2 SCI Interrupts
        1. 27.2.2.1 Transmit Interrupt
        2. 27.2.2.2 Receive Interrupt
        3. 27.2.2.3 WakeUp Interrupt
        4. 27.2.2.4 Error Interrupts
      3. 27.2.3 SCI DMA Interface
        1. 27.2.3.1 Receive DMA Requests
        2. 27.2.3.2 Transmit DMA Requests
      4. 27.2.4 SCI Configurations
        1. 27.2.4.1 Receiving Data
          1. 27.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 27.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 27.2.4.2 Transmitting Data
          1. 27.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 27.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 27.2.5 SCI Low-Power Mode
        1. 27.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 27.3 Local Interconnect Network Module
      1. 27.3.1 LIN Communication Formats
        1. 27.3.1.1  LIN Standards
        2. 27.3.1.2  Message Frame
          1. 27.3.1.2.1 Message Header
          2. 27.3.1.2.2 Response
        3. 27.3.1.3  Synchronizer
        4. 27.3.1.4  Baud Rate
          1. 27.3.1.4.1 Fractional Divider
          2. 27.3.1.4.2 Superfractional Divider
            1. 27.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 27.3.1.5  Header Generation
          1. 27.3.1.5.1 Event Triggered Frame Handling
          2. 27.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 27.3.1.6  Extended Frames Handling
        7. 27.3.1.7  Timeout Control
          1. 27.3.1.7.1 No-Response Error (NRE)
          2. 27.3.1.7.2 Bus Idle Detection
          3. 27.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 27.3.1.8  TXRX Error Detector (TED)
          1. 27.3.1.8.1 Bit Errors
          2. 27.3.1.8.2 Physical Bus Errors
          3. 27.3.1.8.3 ID Parity Errors
          4. 27.3.1.8.4 Checksum Errors
        9. 27.3.1.9  Message Filtering and Validation
        10. 27.3.1.10 Receive Buffers
        11. 27.3.1.11 Transmit Buffers
      2. 27.3.2 LIN Interrupts
      3. 27.3.3 Servicing LIN Interrupts
      4. 27.3.4 LIN DMA Interface
        1. 27.3.4.1 LIN Receive DMA Requests
        2. 27.3.4.2 LIN Transmit DMA Requests
      5. 27.3.5 LIN Configurations
        1. 27.3.5.1 Receiving Data
          1. 27.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 27.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 27.3.5.2 Transmitting Data
          1. 27.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 27.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 27.4 Low-Power Mode
      1. 27.4.1 Entering Sleep Mode
      2. 27.4.2 Wakeup
      3. 27.4.3 Wakeup Timeouts
    5. 27.5 Emulation Mode
    6. 27.6 Software
      1. 27.6.1 LIN Examples
        1. 27.6.1.1 LIN Internal Loopback with Interrupts
        2. 27.6.1.2 LIN SCI Mode Internal Loopback with Interrupts
        3. 27.6.1.3 LIN SCI MODE Internal Loopback with DMA
        4. 27.6.1.4 LIN Internal Loopback without interrupts(polled mode)
        5. 27.6.1.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA
    7. 27.7 SCI/LIN Registers
      1. 27.7.1 LIN Base Address Table
      2. 27.7.2 LIN_REGS Registers
      3. 27.7.3 LIN Registers to Driverlib Functions
  30. 28Fast Serial Interface (FSI)
    1. 28.1 Introduction
      1. 28.1.1 FSI Related Collateral
      2. 28.1.2 FSI Features
    2. 28.2 System-level Integration
      1. 28.2.1 CPU Interface
      2. 28.2.2 Signal Description
        1. 28.2.2.1 Configuring Device Pins
      3. 28.2.3 FSI Interrupts
        1. 28.2.3.1 Transmitter Interrupts
        2. 28.2.3.2 Receiver Interrupts
        3. 28.2.3.3 Configuring Interrupts
        4. 28.2.3.4 Handling Interrupts
      4. 28.2.4 CLA Task Triggering
      5. 28.2.5 DMA Interface
      6. 28.2.6 External Frame Trigger Mux
    3. 28.3 FSI Functional Description
      1. 28.3.1  Introduction to Operation
      2. 28.3.2  FSI Transmitter Module
        1. 28.3.2.1 Initialization
        2. 28.3.2.2 FSI_TX Clocking
        3. 28.3.2.3 Transmitting Frames
          1. 28.3.2.3.1 Software Triggered Frames
          2. 28.3.2.3.2 Externally Triggered Frames
          3. 28.3.2.3.3 Ping Frame Generation
            1. 28.3.2.3.3.1 Automatic Ping Frames
            2. 28.3.2.3.3.2 Software Triggered Ping Frame
            3. 28.3.2.3.3.3 Externally Triggered Ping Frame
          4. 28.3.2.3.4 Transmitting Frames with DMA
        4. 28.3.2.4 Transmit Buffer Management
        5. 28.3.2.5 CRC Submodule
        6. 28.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 28.3.2.7 Reset
      3. 28.3.3  FSI Receiver Module
        1. 28.3.3.1  Initialization
        2. 28.3.3.2  FSI_RX Clocking
        3. 28.3.3.3  Receiving Frames
          1. 28.3.3.3.1 Receiving Frames with DMA
        4. 28.3.3.4  Ping Frame Watchdog
        5. 28.3.3.5  Frame Watchdog
        6. 28.3.3.6  Delay Line Control
        7. 28.3.3.7  Buffer Management
        8. 28.3.3.8  CRC Submodule
        9. 28.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 28.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 28.3.3.11 FSI_RX Reset
      4. 28.3.4  Frame Format
        1. 28.3.4.1 FSI Frame Phases
        2. 28.3.4.2 Frame Types
          1. 28.3.4.2.1 Ping Frames
          2. 28.3.4.2.2 Error Frames
          3. 28.3.4.2.3 Data Frames
        3. 28.3.4.3 Multi-Lane Transmission
      5. 28.3.5  Flush Sequence
      6. 28.3.6  Internal Loopback
      7. 28.3.7  CRC Generation
      8. 28.3.8  ECC Module
      9. 28.3.9  FSI Trigger Generation
      10. 28.3.10 FSI-SPI Compatibility Mode
        1. 28.3.10.1 Available SPI Modes
          1. 28.3.10.1.1 FSITX as SPI Master, Transmit Only
            1. 28.3.10.1.1.1 Initialization
            2. 28.3.10.1.1.2 Operation
          2. 28.3.10.1.2 FSIRX as SPI Slave, Receive Only
            1. 28.3.10.1.2.1 Initialization
            2. 28.3.10.1.2.2 Operation
          3. 28.3.10.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Master
            1. 28.3.10.1.3.1 Initialization
            2. 28.3.10.1.3.2 Operation
    4. 28.4 FSI Programing Guide
      1. 28.4.1 Establishing the Communication Link
        1. 28.4.1.1 Establishing the Communication Link from the Master Device
        2. 28.4.1.2 Establishing the Communication Link from the Slave Device
      2. 28.4.2 Register Protection
      3. 28.4.3 Emulation Mode
    5. 28.5 Software
      1. 28.5.1 FSI Examples
        1. 28.5.1.1  FSI Loopback:CPU Control
        2. 28.5.1.2  FSI Loopback CLA control
        3. 28.5.1.3  FSI DMA frame transfers:DMA Control
        4. 28.5.1.4  FSI data transfer by external trigger
        5. 28.5.1.5  FSI data transfers upon CPU Timer event
        6. 28.5.1.6  FSI and SPI communication(fsi_ex6_spi_main_tx)
        7. 28.5.1.7  FSI and SPI communication(fsi_ex7_spi_remote_rx)
        8. 28.5.1.8  FSI P2Point Connection:Rx Side
        9. 28.5.1.9  FSI P2Point Connection:Tx Side
        10. 28.5.1.10 FSI and SPI communication (fsi_ex9_spi_master_tx_drivers)
        11. 28.5.1.11 FSI and SPI communication (fsi_ex10_spi_slave_rx_driver)
        12. 28.5.1.12 FSI and SPI communication full-duplex
        13. 28.5.1.13 FSI Receive Skew Compensation Block Element Delays
        14. 28.5.1.14 FSI Skew Calibration in Single Data Line Mode (RX Device)
        15. 28.5.1.15 FSI Skew Calibration in Single Data Line Mode (TX Device)
        16. 28.5.1.16 FSI Skew Calibration in Dual Data Line Mode (RX Device)
        17. 28.5.1.17 FSI Skew Calibration in Dual Data Line Mode (TX Device)
        18. 28.5.1.18 FSI Find Optimal Number of Delay Elements Activated For FSIRX
        19. 28.5.1.19 FSI Find Optimal Number of Delay Elements Activated For FSIRX
        20. 28.5.1.20 FSI daisy chain topology, lead device example
        21. 28.5.1.21 FSI daisy chain topology, node device example
    6. 28.6 FSI Registers
      1. 28.6.1 FSI Base Address Table
      2. 28.6.2 FSI_TX_REGS Registers
      3. 28.6.3 FSI_RX_REGS Registers
      4. 28.6.4 FSI Registers to Driverlib Functions
  31. 29Configurable Logic Block (CLB)
    1. 29.1 Introduction
      1. 29.1.1 CLB Related Collateral
    2. 29.2 Description
      1. 29.2.1 CLB Clock
    3. 29.3 CLB Input/Output Connection
      1. 29.3.1 Overview
      2. 29.3.2 CLB Input Selection
      3. 29.3.3 CLB Output Selection
      4. 29.3.4 CLB Output Signal Multiplexer
    4. 29.4 CLB Tile
      1. 29.4.1 Static Switch Block
      2. 29.4.2 Counter Block
        1. 29.4.2.1 Counter Description
        2. 29.4.2.2 Counter Operation
        3. 29.4.2.3 Serializer Mode
        4. 29.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 29.4.3 FSM Block
      4. 29.4.4 LUT4 Block
      5. 29.4.5 Output LUT Block
      6. 29.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 29.4.7 High Level Controller (HLC)
        1. 29.4.7.1 High Level Controller Events
        2. 29.4.7.2 High Level Controller Instructions
        3. 29.4.7.3 <Src> and <Dest>
        4. 29.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 29.5 CPU Interface
      1. 29.5.1 Register Description
      2. 29.5.2 Non-Memory Mapped Registers
    6. 29.6 DMA Access
    7. 29.7 Software
      1. 29.7.1 CLB Examples
        1. 29.7.1.1  CLB Empty Project
        2. 29.7.1.2  CLB Combinational Logic
        3. 29.7.1.3  CLB GPIO Input Filter
        4. 29.7.1.4  CLB Auxilary PWM
        5. 29.7.1.5  CLB PWM Protection
        6. 29.7.1.6  CLB Event Window
        7. 29.7.1.7  CLB Signal Generator
        8. 29.7.1.8  CLB State Machine
        9. 29.7.1.9  CLB External Signal AND Gate
        10. 29.7.1.10 CLB Timer
        11. 29.7.1.11 CLB Timer Two States
        12. 29.7.1.12 CLB Interrupt Tag
        13. 29.7.1.13 CLB Output Intersect
        14. 29.7.1.14 CLB PUSH PULL
        15. 29.7.1.15 CLB Multi Tile
        16. 29.7.1.16 CLB Glue Logic
        17. 29.7.1.17 CLB based One-shot PWM
        18. 29.7.1.18 CLB AOC Control
        19. 29.7.1.19 CLB AOC Release Control
        20. 29.7.1.20 CLB AOC Control
        21. 29.7.1.21 CLB Serializer
        22. 29.7.1.22 CLB LFSR
        23. 29.7.1.23 CLB Trip Zone Timestamp
        24. 29.7.1.24 CLB CRC
    8. 29.8 CLB Registers
      1. 29.8.1 CLB Base Addresses
      2. 29.8.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 29.8.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 29.8.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 29.8.5 CLB Registers to Driverlib Functions
  32. 30Revision History

8.9.3 GPIO_DATA_REGS Registers

Table 8-54 lists the memory-mapped registers for the GPIO_DATA_REGS registers. All register offset addresses not listed in Table 8-54 should be considered as reserved locations and the register contents should not be modified.

Table 8-54 GPIO_DATA_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hGPADATGPIO A Data Register (GPIO0 to GPIO31)Go
2hGPASETGPIO A Output Set (GPIO0 to GPIO31)Go
4hGPACLEARGPIO A Output Clear (GPIO0 to GPIO31)Go
6hGPATOGGLEGPIO A Output Toggle (GPIO0 to GPIO31)Go
8hGPBDATGPIO B Data Register (GPIO32 to GPIO64)Go
AhGPBSETGPIO B Output Set (GPIO32 to GPIO64)Go
ChGPBCLEARGPIO B Output Clear (GPIO32 to GPIO64)Go
EhGPBTOGGLEGPIO B Output Toggle (GPIO32 to GPIO64)Go
38hGPHDATGPIO H Data Register (GPIO0 to GPIO255)Go

Complex bit access types are encoded to fit into small table cells. Table 8-55 shows the codes that are used for access types in this section.

Table 8-55 GPIO_DATA_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

8.9.3.1 GPADAT Register (Offset = 0h) [Reset = 00000000h]

GPADAT is shown in Figure 8-47 and described in Table 8-56.

Return to the Summary Table.

GPIO A Data (GPIO0 to GPIO31)

Reading a field in this register returns the input level of the corresponding IO pin after qualification and (optionally) inversion. The input value is always readable even when the pin is configured as a GPIO output or peripheral signal.

Writing to a field in this register selects the value of the output data latch for the corresponding IO pin. If the pin is configured as a GPIO output, this value will be driven onto the pin. Otherwise, the value will be latched and ignored unless the pin is reconfigured to be an output. A system reset will clear all output latches.

Due to the difference between the read and write values, sequential read-modify-write operations on this register may corrupt the state of the output latches. The GPASET, GPACLEAR, and GPATOGGLE registers should be used to safely control the output latches.

Figure 8-47 GPADAT Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-56 GPADAT Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hRead: Input value, Write: Output latch for GPIO31

Reset type: SYSRSn

30GPIO30R/W0hRead: Input value, Write: Output latch for GPIO30

Reset type: SYSRSn

29GPIO29R/W0hRead: Input value, Write: Output latch for GPIO29

Reset type: SYSRSn

28GPIO28R/W0hRead: Input value, Write: Output latch for GPIO28

Reset type: SYSRSn

27GPIO27R/W0hRead: Input value, Write: Output latch for GPIO27

Reset type: SYSRSn

26GPIO26R/W0hRead: Input value, Write: Output latch for GPIO26

Reset type: SYSRSn

25GPIO25R/W0hRead: Input value, Write: Output latch for GPIO25

Reset type: SYSRSn

24GPIO24R/W0hRead: Input value, Write: Output latch for GPIO24

Reset type: SYSRSn

23GPIO23R/W0hRead: Input value, Write: Output latch for GPIO23

Reset type: SYSRSn

22GPIO22R/W0hRead: Input value, Write: Output latch for GPIO22

Reset type: SYSRSn

21GPIO21R/W0hRead: Input value, Write: Output latch for GPIO21

Reset type: SYSRSn

20GPIO20R/W0hRead: Input value, Write: Output latch for GPIO20

Reset type: SYSRSn

19GPIO19R/W0hRead: Input value, Write: Output latch for GPIO19

Reset type: SYSRSn

18GPIO18R/W0hRead: Input value, Write: Output latch for GPIO18

Reset type: SYSRSn

17GPIO17R/W0hRead: Input value, Write: Output latch for GPIO17

Reset type: SYSRSn

16GPIO16R/W0hRead: Input value, Write: Output latch for GPIO16

Reset type: SYSRSn

15GPIO15R/W0hRead: Input value, Write: Output latch for GPIO15

Reset type: SYSRSn

14GPIO14R/W0hRead: Input value, Write: Output latch for GPIO14

Reset type: SYSRSn

13GPIO13R/W0hRead: Input value, Write: Output latch for GPIO13

Reset type: SYSRSn

12GPIO12R/W0hRead: Input value, Write: Output latch for GPIO12

Reset type: SYSRSn

11GPIO11R/W0hRead: Input value, Write: Output latch for GPIO11

Reset type: SYSRSn

10GPIO10R/W0hRead: Input value, Write: Output latch for GPIO10

Reset type: SYSRSn

9GPIO9R/W0hRead: Input value, Write: Output latch for GPIO9

Reset type: SYSRSn

8GPIO8R/W0hRead: Input value, Write: Output latch for GPIO8

Reset type: SYSRSn

7GPIO7R/W0hRead: Input value, Write: Output latch for GPIO7

Reset type: SYSRSn

6GPIO6R/W0hRead: Input value, Write: Output latch for GPIO6

Reset type: SYSRSn

5GPIO5R/W0hRead: Input value, Write: Output latch for GPIO5

Reset type: SYSRSn

4GPIO4R/W0hRead: Input value, Write: Output latch for GPIO4

Reset type: SYSRSn

3GPIO3R/W0hRead: Input value, Write: Output latch for GPIO3

Reset type: SYSRSn

2GPIO2R/W0hRead: Input value, Write: Output latch for GPIO2

Reset type: SYSRSn

1GPIO1R/W0hRead: Input value, Write: Output latch for GPIO1

Reset type: SYSRSn

0GPIO0R/W0hRead: Input value, Write: Output latch for GPIO0

Reset type: SYSRSn

8.9.3.2 GPASET Register (Offset = 2h) [Reset = 00000000h]

GPASET is shown in Figure 8-48 and described in Table 8-57.

Return to the Summary Table.

GPIO Output Set (GPIO0 to GPIO31)

Writing a 1 to a field in this register sets the output data latch for the corresponding IO pin. Writes of 0 are ignored. Reads of this register always return 0.

Figure 8-48 GPASET Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-57 GPASET Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutput set for GPIO31

Reset type: SYSRSn

30GPIO30R/W0hOutput set for GPIO30

Reset type: SYSRSn

29GPIO29R/W0hOutput set for GPIO29

Reset type: SYSRSn

28GPIO28R/W0hOutput set for GPIO28

Reset type: SYSRSn

27GPIO27R/W0hOutput set for GPIO27

Reset type: SYSRSn

26GPIO26R/W0hOutput set for GPIO26

Reset type: SYSRSn

25GPIO25R/W0hOutput set for GPIO25

Reset type: SYSRSn

24GPIO24R/W0hOutput set for GPIO24

Reset type: SYSRSn

23GPIO23R/W0hOutput set for GPIO23

Reset type: SYSRSn

22GPIO22R/W0hOutput set for GPIO22

Reset type: SYSRSn

21GPIO21R/W0hOutput set for GPIO21

Reset type: SYSRSn

20GPIO20R/W0hOutput set for GPIO20

Reset type: SYSRSn

19GPIO19R/W0hOutput set for GPIO19

Reset type: SYSRSn

18GPIO18R/W0hOutput set for GPIO18

Reset type: SYSRSn

17GPIO17R/W0hOutput set for GPIO17

Reset type: SYSRSn

16GPIO16R/W0hOutput set for GPIO16

Reset type: SYSRSn

15GPIO15R/W0hOutput set for GPIO15

Reset type: SYSRSn

14GPIO14R/W0hOutput set for GPIO14

Reset type: SYSRSn

13GPIO13R/W0hOutput set for GPIO13

Reset type: SYSRSn

12GPIO12R/W0hOutput set for GPIO12

Reset type: SYSRSn

11GPIO11R/W0hOutput set for GPIO11

Reset type: SYSRSn

10GPIO10R/W0hOutput set for GPIO10

Reset type: SYSRSn

9GPIO9R/W0hOutput set for GPIO9

Reset type: SYSRSn

8GPIO8R/W0hOutput set for GPIO8

Reset type: SYSRSn

7GPIO7R/W0hOutput set for GPIO7

Reset type: SYSRSn

6GPIO6R/W0hOutput set for GPIO6

Reset type: SYSRSn

5GPIO5R/W0hOutput set for GPIO5

Reset type: SYSRSn

4GPIO4R/W0hOutput set for GPIO4

Reset type: SYSRSn

3GPIO3R/W0hOutput set for GPIO3

Reset type: SYSRSn

2GPIO2R/W0hOutput set for GPIO2

Reset type: SYSRSn

1GPIO1R/W0hOutput set for GPIO1

Reset type: SYSRSn

0GPIO0R/W0hOutput set for GPIO0

Reset type: SYSRSn

8.9.3.3 GPACLEAR Register (Offset = 4h) [Reset = 00000000h]

GPACLEAR is shown in Figure 8-49 and described in Table 8-58.

Return to the Summary Table.

GPIO Output Clear (GPIO0 to GPIO31)

Writing a 1 to a field in this register clears the output data latch for the corresponding IO pin. Writes of 0 are ignored. Reads of this register always return 0.

Figure 8-49 GPACLEAR Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-58 GPACLEAR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutput clear for GPIO31

Reset type: SYSRSn

30GPIO30R/W0hOutput clear for GPIO30

Reset type: SYSRSn

29GPIO29R/W0hOutput clear for GPIO29

Reset type: SYSRSn

28GPIO28R/W0hOutput clear for GPIO28

Reset type: SYSRSn

27GPIO27R/W0hOutput clear for GPIO27

Reset type: SYSRSn

26GPIO26R/W0hOutput clear for GPIO26

Reset type: SYSRSn

25GPIO25R/W0hOutput clear for GPIO25

Reset type: SYSRSn

24GPIO24R/W0hOutput clear for GPIO24

Reset type: SYSRSn

23GPIO23R/W0hOutput clear for GPIO23

Reset type: SYSRSn

22GPIO22R/W0hOutput clear for GPIO22

Reset type: SYSRSn

21GPIO21R/W0hOutput clear for GPIO21

Reset type: SYSRSn

20GPIO20R/W0hOutput clear for GPIO20

Reset type: SYSRSn

19GPIO19R/W0hOutput clear for GPIO19

Reset type: SYSRSn

18GPIO18R/W0hOutput clear for GPIO18

Reset type: SYSRSn

17GPIO17R/W0hOutput clear for GPIO17

Reset type: SYSRSn

16GPIO16R/W0hOutput clear for GPIO16

Reset type: SYSRSn

15GPIO15R/W0hOutput clear for GPIO15

Reset type: SYSRSn

14GPIO14R/W0hOutput clear for GPIO14

Reset type: SYSRSn

13GPIO13R/W0hOutput clear for GPIO13

Reset type: SYSRSn

12GPIO12R/W0hOutput clear for GPIO12

Reset type: SYSRSn

11GPIO11R/W0hOutput clear for GPIO11

Reset type: SYSRSn

10GPIO10R/W0hOutput clear for GPIO10

Reset type: SYSRSn

9GPIO9R/W0hOutput clear for GPIO9

Reset type: SYSRSn

8GPIO8R/W0hOutput clear for GPIO8

Reset type: SYSRSn

7GPIO7R/W0hOutput clear for GPIO7

Reset type: SYSRSn

6GPIO6R/W0hOutput clear for GPIO6

Reset type: SYSRSn

5GPIO5R/W0hOutput clear for GPIO5

Reset type: SYSRSn

4GPIO4R/W0hOutput clear for GPIO4

Reset type: SYSRSn

3GPIO3R/W0hOutput clear for GPIO3

Reset type: SYSRSn

2GPIO2R/W0hOutput clear for GPIO2

Reset type: SYSRSn

1GPIO1R/W0hOutput clear for GPIO1

Reset type: SYSRSn

0GPIO0R/W0hOutput clear for GPIO0

Reset type: SYSRSn

8.9.3.4 GPATOGGLE Register (Offset = 6h) [Reset = 00000000h]

GPATOGGLE is shown in Figure 8-50 and described in Table 8-59.

Return to the Summary Table.

GPIO Output Toggle (GPIO0 to GPIO31)

Writing a 1 to a field in this register inverts the value of the output data latch for the corresponding IO pin. Writes of 0 are ignored. Reads of this register always return 0.

Figure 8-50 GPATOGGLE Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-59 GPATOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutput toggle for GPIO31

Reset type: SYSRSn

30GPIO30R/W0hOutput toggle for GPIO30

Reset type: SYSRSn

29GPIO29R/W0hOutput toggle for GPIO29

Reset type: SYSRSn

28GPIO28R/W0hOutput toggle for GPIO28

Reset type: SYSRSn

27GPIO27R/W0hOutput toggle for GPIO27

Reset type: SYSRSn

26GPIO26R/W0hOutput toggle for GPIO26

Reset type: SYSRSn

25GPIO25R/W0hOutput toggle for GPIO25

Reset type: SYSRSn

24GPIO24R/W0hOutput toggle for GPIO24

Reset type: SYSRSn

23GPIO23R/W0hOutput toggle for GPIO23

Reset type: SYSRSn

22GPIO22R/W0hOutput toggle for GPIO22

Reset type: SYSRSn

21GPIO21R/W0hOutput toggle for GPIO21

Reset type: SYSRSn

20GPIO20R/W0hOutput toggle for GPIO20

Reset type: SYSRSn

19GPIO19R/W0hOutput toggle for GPIO19

Reset type: SYSRSn

18GPIO18R/W0hOutput toggle for GPIO18

Reset type: SYSRSn

17GPIO17R/W0hOutput toggle for GPIO17

Reset type: SYSRSn

16GPIO16R/W0hOutput toggle for GPIO16

Reset type: SYSRSn

15GPIO15R/W0hOutput toggle for GPIO15

Reset type: SYSRSn

14GPIO14R/W0hOutput toggle for GPIO14

Reset type: SYSRSn

13GPIO13R/W0hOutput toggle for GPIO13

Reset type: SYSRSn

12GPIO12R/W0hOutput toggle for GPIO12

Reset type: SYSRSn

11GPIO11R/W0hOutput toggle for GPIO11

Reset type: SYSRSn

10GPIO10R/W0hOutput toggle for GPIO10

Reset type: SYSRSn

9GPIO9R/W0hOutput toggle for GPIO9

Reset type: SYSRSn

8GPIO8R/W0hOutput toggle for GPIO8

Reset type: SYSRSn

7GPIO7R/W0hOutput toggle for GPIO7

Reset type: SYSRSn

6GPIO6R/W0hOutput toggle for GPIO6

Reset type: SYSRSn

5GPIO5R/W0hOutput toggle for GPIO5

Reset type: SYSRSn

4GPIO4R/W0hOutput toggle for GPIO4

Reset type: SYSRSn

3GPIO3R/W0hOutput toggle for GPIO3

Reset type: SYSRSn

2GPIO2R/W0hOutput toggle for GPIO2

Reset type: SYSRSn

1GPIO1R/W0hOutput toggle for GPIO1

Reset type: SYSRSn

0GPIO0R/W0hOutput toggle for GPIO0

Reset type: SYSRSn

8.9.3.5 GPBDAT Register (Offset = 8h) [Reset = 00000000h]

GPBDAT is shown in Figure 8-51 and described in Table 8-60.

Return to the Summary Table.

GPIO B Data (GPIO32 to GPIO64)

Reading a field in this register returns the input level of the corresponding IO pin after qualification and (optionally) inversion. The input value is always readable even when the pin is configured as a GPIO output or peripheral signal.

Writing to a field in this register selects the value of the output data latch for the corresponding IO pin. If the pin is configured as a GPIO output, this value will be driven onto the pin. Otherwise, the value will be latched and ignored unless the pin is reconfigured to be an output. A system reset will clear all output latches.

Due to the difference between the read and write values, sequential read-modify-write operations on this register may corrupt the state of the output latches. The GPBSET, GPBCLEAR, and GPBTOGGLE registers should be used to safely control the output latches.

Figure 8-51 GPBDAT Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDGPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39RESERVEDGPIO37RESERVEDGPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-60 GPBDAT Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27GPIO59R/W0hRead: Input value, Write: Output latch for GPIO59

Reset type: SYSRSn

26GPIO58R/W0hRead: Input value, Write: Output latch for GPIO58

Reset type: SYSRSn

25GPIO57R/W0hRead: Input value, Write: Output latch for GPIO57

Reset type: SYSRSn

24GPIO56R/W0hRead: Input value, Write: Output latch for GPIO56

Reset type: SYSRSn

23GPIO55R/W0hRead: Input value, Write: Output latch for GPIO55

Reset type: SYSRSn

22GPIO54R/W0hRead: Input value, Write: Output latch for GPIO54

Reset type: SYSRSn

21GPIO53R/W0hRead: Input value, Write: Output latch for GPIO53

Reset type: SYSRSn

20GPIO52R/W0hRead: Input value, Write: Output latch for GPIO52

Reset type: SYSRSn

19GPIO51R/W0hRead: Input value, Write: Output latch for GPIO51

Reset type: SYSRSn

18GPIO50R/W0hRead: Input value, Write: Output latch for GPIO50

Reset type: SYSRSn

17GPIO49R/W0hRead: Input value, Write: Output latch for GPIO49

Reset type: SYSRSn

16GPIO48R/W0hRead: Input value, Write: Output latch for GPIO48

Reset type: SYSRSn

15GPIO47R/W0hRead: Input value, Write: Output latch for GPIO47

Reset type: SYSRSn

14GPIO46R/W0hRead: Input value, Write: Output latch for GPIO46

Reset type: SYSRSn

13GPIO45R/W0hRead: Input value, Write: Output latch for GPIO45

Reset type: SYSRSn

12GPIO44R/W0hRead: Input value, Write: Output latch for GPIO44

Reset type: SYSRSn

11GPIO43R/W0hRead: Input value, Write: Output latch for GPIO43

Reset type: SYSRSn

10GPIO42R/W0hRead: Input value, Write: Output latch for GPIO42

Reset type: SYSRSn

9GPIO41R/W0hRead: Input value, Write: Output latch for GPIO41

Reset type: SYSRSn

8GPIO40R/W0hRead: Input value, Write: Output latch for GPIO40

Reset type: SYSRSn

7GPIO39R/W0hRead: Input value, Write: Output latch for GPIO39

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO37R/W0hRead: Input value, Write: Output latch for GPIO37

Reset type: SYSRSn

4RESERVEDR/W0hReserved
3GPIO35R/W0hRead: Input value, Write: Output latch for GPIO35

Reset type: SYSRSn

2GPIO34R/W0hRead: Input value, Write: Output latch for GPIO34

Reset type: SYSRSn

1GPIO33R/W0hRead: Input value, Write: Output latch for GPIO33

Reset type: SYSRSn

0GPIO32R/W0hRead: Input value, Write: Output latch for GPIO32

Reset type: SYSRSn

8.9.3.6 GPBSET Register (Offset = Ah) [Reset = 00000000h]

GPBSET is shown in Figure 8-52 and described in Table 8-61.

Return to the Summary Table.

GPIO Output Set (GPIO32 to GPIO64)

Writing a 1 to a field in this register sets the output data latch for the corresponding IO pin. Writes of 0 are ignored. Reads of this register always return 0.

Figure 8-52 GPBSET Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDGPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39RESERVEDGPIO37RESERVEDGPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-61 GPBSET Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27GPIO59R/W0hOutput set for GPIO59

Reset type: SYSRSn

26GPIO58R/W0hOutput set for GPIO58

Reset type: SYSRSn

25GPIO57R/W0hOutput set for GPIO57

Reset type: SYSRSn

24GPIO56R/W0hOutput set for GPIO56

Reset type: SYSRSn

23GPIO55R/W0hOutput set for GPIO55

Reset type: SYSRSn

22GPIO54R/W0hOutput set for GPIO54

Reset type: SYSRSn

21GPIO53R/W0hOutput set for GPIO53

Reset type: SYSRSn

20GPIO52R/W0hOutput set for GPIO52

Reset type: SYSRSn

19GPIO51R/W0hOutput set for GPIO51

Reset type: SYSRSn

18GPIO50R/W0hOutput set for GPIO50

Reset type: SYSRSn

17GPIO49R/W0hOutput set for GPIO49

Reset type: SYSRSn

16GPIO48R/W0hOutput set for GPIO48

Reset type: SYSRSn

15GPIO47R/W0hOutput set for GPIO47

Reset type: SYSRSn

14GPIO46R/W0hOutput set for GPIO46

Reset type: SYSRSn

13GPIO45R/W0hOutput set for GPIO45

Reset type: SYSRSn

12GPIO44R/W0hOutput set for GPIO44

Reset type: SYSRSn

11GPIO43R/W0hOutput set for GPIO43

Reset type: SYSRSn

10GPIO42R/W0hOutput set for GPIO42

Reset type: SYSRSn

9GPIO41R/W0hOutput set for GPIO41

Reset type: SYSRSn

8GPIO40R/W0hOutput set for GPIO40

Reset type: SYSRSn

7GPIO39R/W0hOutput set for GPIO39

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO37R/W0hOutput set for GPIO37

Reset type: SYSRSn

4RESERVEDR/W0hReserved
3GPIO35R/W0hOutput set for GPIO35

Reset type: SYSRSn

2GPIO34R/W0hOutput set for GPIO34

Reset type: SYSRSn

1GPIO33R/W0hOutput set for GPIO33

Reset type: SYSRSn

0GPIO32R/W0hOutput set for GPIO32

Reset type: SYSRSn

8.9.3.7 GPBCLEAR Register (Offset = Ch) [Reset = 00000000h]

GPBCLEAR is shown in Figure 8-53 and described in Table 8-62.

Return to the Summary Table.

GPIO Output Clear (GPIO32 to GPIO64)

Writing a 1 to a field in this register clears the output data latch for the corresponding IO pin. Writes of 0 are ignored. Reads of this register always return 0.

Figure 8-53 GPBCLEAR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDGPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39RESERVEDGPIO37RESERVEDGPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-62 GPBCLEAR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27GPIO59R/W0hOutput clear for GPIO59

Reset type: SYSRSn

26GPIO58R/W0hOutput clear for GPIO58

Reset type: SYSRSn

25GPIO57R/W0hOutput clear for GPIO57

Reset type: SYSRSn

24GPIO56R/W0hOutput clear for GPIO56

Reset type: SYSRSn

23GPIO55R/W0hOutput clear for GPIO55

Reset type: SYSRSn

22GPIO54R/W0hOutput clear for GPIO54

Reset type: SYSRSn

21GPIO53R/W0hOutput clear for GPIO53

Reset type: SYSRSn

20GPIO52R/W0hOutput clear for GPIO52

Reset type: SYSRSn

19GPIO51R/W0hOutput clear for GPIO51

Reset type: SYSRSn

18GPIO50R/W0hOutput clear for GPIO50

Reset type: SYSRSn

17GPIO49R/W0hOutput clear for GPIO49

Reset type: SYSRSn

16GPIO48R/W0hOutput clear for GPIO48

Reset type: SYSRSn

15GPIO47R/W0hOutput clear for GPIO47

Reset type: SYSRSn

14GPIO46R/W0hOutput clear for GPIO46

Reset type: SYSRSn

13GPIO45R/W0hOutput clear for GPIO45

Reset type: SYSRSn

12GPIO44R/W0hOutput clear for GPIO44

Reset type: SYSRSn

11GPIO43R/W0hOutput clear for GPIO43

Reset type: SYSRSn

10GPIO42R/W0hOutput clear for GPIO42

Reset type: SYSRSn

9GPIO41R/W0hOutput clear for GPIO41

Reset type: SYSRSn

8GPIO40R/W0hOutput clear for GPIO40

Reset type: SYSRSn

7GPIO39R/W0hOutput clear for GPIO39

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO37R/W0hOutput clear for GPIO37

Reset type: SYSRSn

4RESERVEDR/W0hReserved
3GPIO35R/W0hOutput clear for GPIO35

Reset type: SYSRSn

2GPIO34R/W0hOutput clear for GPIO34

Reset type: SYSRSn

1GPIO33R/W0hOutput clear for GPIO33

Reset type: SYSRSn

0GPIO32R/W0hOutput clear for GPIO32

Reset type: SYSRSn

8.9.3.8 GPBTOGGLE Register (Offset = Eh) [Reset = 00000000h]

GPBTOGGLE is shown in Figure 8-54 and described in Table 8-63.

Return to the Summary Table.

GPIO Output Toggle (GPIO32 to GPIO64)

Writing a 1 to a field in this register inverts the value of the output data latch for the corresponding IO pin. Writes of 0 are ignored. Reads of this register always return 0.

Figure 8-54 GPBTOGGLE Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDGPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39RESERVEDGPIO37RESERVEDGPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-63 GPBTOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27GPIO59R/W0hOutput toggle for GPIO59

Reset type: SYSRSn

26GPIO58R/W0hOutput toggle for GPIO58

Reset type: SYSRSn

25GPIO57R/W0hOutput toggle for GPIO57

Reset type: SYSRSn

24GPIO56R/W0hOutput toggle for GPIO56

Reset type: SYSRSn

23GPIO55R/W0hOutput toggle for GPIO55

Reset type: SYSRSn

22GPIO54R/W0hOutput toggle for GPIO54

Reset type: SYSRSn

21GPIO53R/W0hOutput toggle for GPIO53

Reset type: SYSRSn

20GPIO52R/W0hOutput toggle for GPIO52

Reset type: SYSRSn

19GPIO51R/W0hOutput toggle for GPIO51

Reset type: SYSRSn

18GPIO50R/W0hOutput toggle for GPIO50

Reset type: SYSRSn

17GPIO49R/W0hOutput toggle for GPIO49

Reset type: SYSRSn

16GPIO48R/W0hOutput toggle for GPIO48

Reset type: SYSRSn

15GPIO47R/W0hOutput toggle for GPIO47

Reset type: SYSRSn

14GPIO46R/W0hOutput toggle for GPIO46

Reset type: SYSRSn

13GPIO45R/W0hOutput toggle for GPIO45

Reset type: SYSRSn

12GPIO44R/W0hOutput toggle for GPIO44

Reset type: SYSRSn

11GPIO43R/W0hOutput toggle for GPIO43

Reset type: SYSRSn

10GPIO42R/W0hOutput toggle for GPIO42

Reset type: SYSRSn

9GPIO41R/W0hOutput toggle for GPIO41

Reset type: SYSRSn

8GPIO40R/W0hOutput toggle for GPIO40

Reset type: SYSRSn

7GPIO39R/W0hOutput toggle for GPIO39

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO37R/W0hOutput toggle for GPIO37

Reset type: SYSRSn

4RESERVEDR/W0hReserved
3GPIO35R/W0hOutput toggle for GPIO35

Reset type: SYSRSn

2GPIO34R/W0hOutput toggle for GPIO34

Reset type: SYSRSn

1GPIO33R/W0hOutput toggle for GPIO33

Reset type: SYSRSn

0GPIO32R/W0hOutput toggle for GPIO32

Reset type: SYSRSn

8.9.3.9 GPHDAT Register (Offset = 38h) [Reset = 00000000h]

GPHDAT is shown in Figure 8-55 and described in Table 8-64.

Return to the Summary Table.

GPIO H Data (GPIO224 to GPIO255)

Reading a field in this register returns the input level of the corresponding IO pin after qualification and (optionally) inversion. In digital mode, these pins only support input functionality.

Figure 8-55 GPHDAT Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO247GPIO246GPIO245GPIO244GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-64 GPHDAT Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23GPIO247R/W0hRead: Input value for GPIO247

Reset type: SYSRSn

22GPIO246R/W0hRead: Input value for GPIO246

Reset type: SYSRSn

21GPIO245R/W0hRead: Input value for GPIO245

Reset type: SYSRSn

20GPIO244R/W0hRead: Input value for GPIO244

Reset type: SYSRSn

19GPIO243R/W0hRead: Input value for GPIO243

Reset type: SYSRSn

18GPIO242R/W0hRead: Input value for GPIO242

Reset type: SYSRSn

17GPIO241R/W0hRead: Input value for GPIO241

Reset type: SYSRSn

16GPIO240R/W0hRead: Input value for GPIO240

Reset type: SYSRSn

15GPIO239R/W0hRead: Input value for GPIO239

Reset type: SYSRSn

14GPIO238R/W0hRead: Input value for GPIO238

Reset type: SYSRSn

13GPIO237R/W0hRead: Input value for GPIO237

Reset type: SYSRSn

12GPIO236R/W0hRead: Input value for GPIO236

Reset type: SYSRSn

11GPIO235R/W0hRead: Input value for GPIO235

Reset type: SYSRSn

10GPIO234R/W0hRead: Input value for GPIO234

Reset type: SYSRSn

9GPIO233R/W0hRead: Input value for GPIO233

Reset type: SYSRSn

8GPIO232R/W0hRead: Input value for GPIO232

Reset type: SYSRSn

7GPIO231R/W0hRead: Input value for GPIO231

Reset type: SYSRSn

6GPIO230R/W0hRead: Input value for GPIO230

Reset type: SYSRSn

5GPIO229R/W0hRead: Input value for GPIO229

Reset type: SYSRSn

4GPIO228R/W0hRead: Input value for GPIO228

Reset type: SYSRSn

3GPIO227R/W0hRead: Input value for GPIO227

Reset type: SYSRSn

2GPIO226R/W0hRead: Input value for GPIO226

Reset type: SYSRSn

1GPIO225R/W0hRead: Input value for GPIO225

Reset type: SYSRSn

0GPIO224R/W0hRead: Input value for GPIO224

Reset type: SYSRSn