SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
The GPIO Output X-BAR has eight outputs that are routed to the GPIO module. Figure 11-5 represents the architecture of a single output, but this output is identical to the architecture of all of the other outputs. Note that the architecture of the Output X-BAR (with the exception of the output latch) is similar to the architecture of the ePWM X-BAR.
First, determine the signals that can be passed to the GPIO by referencing Table 11-5. Select up to one signal per mux (32 total muxes) for each OUTPUTXBARx output. Select the inputs to each mux using the OUTPUTxMUX0TO15CFG and OUTPUTxMUX16TO31CFG registers. To pass any signal through to the GPIO, enable the mux in the OUTPUTxMUXENABLE register. All muxes that are enabled are logically ORed before being passed on to the respective OUTPUTx signal on the GPIO module. To optionally invert the signal, use the OUTPUTINV register. The signal is only recognized on the GPIO, if the proper OUTPUTx muxing options are selected using the GpioCtrlRegs.GPxMUX and GpioCtrlRegs.GPxGMUX registers.
Mux | 0 | 1 | 2 | 3 |
---|---|---|---|---|
G0 | CMPSS1_CTRIPOUTH | CMPSS1_CTRIPOUTH_OR_CTRIPOUTL | ADCAEVT1 | ECAP1_OUT |
G1 | CMPSS1_CTRIPOUTL | INPUTXBAR1 | CLB1_OUT12 | ADCCEVT1 |
G2 | CMPSS2_CTRIPOUTH | CMPSS2_CTRIPOUTH_OR_CTRIPOUTL | ADCAEVT2 | ECAP2_OUT |
G3 | CMPSS2_CTRIPOUTL | INPUTXBAR2 | CLB1_OUT13 | ADCCEVT2 |
G4 | CMPSS3_CTRIPOUTH | CMPSS3_CTRIPOUTH_OR_CTRIPOUTL | ADCAEVT3 | ECAP3_OUT |
G5 | CMPSS3_CTRIPOUTL | INPUTXBAR3 | CLB2_OUT12 | ADCCEVT3 |
G6 | CMPSS4_CTRIPOUTH | CMPSS4_CTRIPOUTH_OR_CTRIPOUTL | ADCAEVT4 | Reserved |
G7 | CMPSS4_CTRIPOUTL | INPUTXBAR4 | CLB2_OUT13 | ADCCEVT4 |
G8 | Reserved | Reserved | ADCBEVT1 | Reserved |
G9 | Reserved | INPUTXBAR5 | CLB3_OUT12 | Reserved |
G10 | Reserved | Reserved | ADCBEVT2 | Reserved |
G11 | Reserved | INPUTXBAR6 | CLB3_OUT13 | Reserved |
G12 | Reserved | Reserved | ADCBEVT3 | Reserved |
G13 | Reserved | ADCSOCAO | CLB4_OUT12 | Reserved |
G14 | Reserved | Reserved | ADCBEVT4 | EXTSYNCOUT |
G15 | Reserved | ADCSOCBO | CLB4_OUT13 | Reserved |
G16 | SD1FLT1_CEVT1 | SD1FLT1_CEVT1_OR_CEVT2 | Reserved | Reserved |
G17 | SD1FLT1_CEVT2 | Reserved | Reserved | CLAHALT |
G18 | SD1FLT2_CEVT1 | SD1FLT2_CEVT1_OR_CEVT2 | Reserved | Reserved |
G19 | SD1FLT2_CEVT2 | Reserved | Reserved | ERRORSTS |
G20 | SD1FLT3_CEVT1 | SD1FLT3_CEVT1_OR_CEVT2 | Reserved | Reserved |
G21 | SD1FLT3_CEVT2 | Reserved | Reserved | FSIRXA_TRIG2 |
G22 | SD1FLT4_CEVT1 | SD1FLT4_CEVT1_OR_CEVT2 | Reserved | Reserved |
G23 | SD1FLT4_CEVT2 | Reserved | Reserved | Reserved |
G24 | SD2FLT1_CEVT1 | SD2FLT1_CEVT1_OR_CEVT2 | Reserved | Reserved |
G25 | SD2FLT1_CEVT2 | Reserved | Reserved | Reserved |
G26 | SD2FLT2_CEVT1 | SD2FLT2_CEVT1_OR_CEVT2 | Reserved | Reserved |
G27 | SD2FLT2_CEVT2 | Reserved | Reserved | Reserved |
G28 | SD2FLT3_CEVT1 | SD2FLT3_CEVT1_OR_CEVT2 | Reserved | Reserved |
G29 | SD2FLT3_CEVT2 | Reserved | Reserved | Reserved |
G30 | SD2FLT4_CEVT1 | SD2FLT4_CEVT1_OR_CEVT2 | Reserved | EPG1OUT0 |
G31 | SD2FLT4_CEVT2 | Reserved | ERRORSTS | EPG1OUT1 |