SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 15-6 lists the memory-mapped registers for the ANALOG_SUBSYS_REGS registers. All register offset addresses not listed in Table 15-6 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
4Ah | INTERNALTESTCTL | INTERNALTEST Node Control Register | EALLOW | Go |
5Eh | CONFIGLOCK | Lock Register for all the config registers. | EALLOW | Go |
60h | TSNSCTL | Temperature Sensor Control Register | EALLOW | Go |
68h | ANAREFCTL | Analog Reference Control Register | EALLOW | Go |
70h | VMONCTL | Voltage Monitor Control Register | EALLOW | Go |
82h | CMPHPMXSEL | Bits to select one of the many sources on CompHP inputs. Refer to Pimux diagram for details. | EALLOW | Go |
84h | CMPLPMXSEL | Bits to select one of the many sources on CompLP inputs. Refer to Pimux diagram for details. | EALLOW | Go |
86h | CMPHNMXSEL | Bits to select one of the many sources on CompHN inputs. Refer to Pimux diagram for details. | EALLOW | Go |
87h | CMPLNMXSEL | Bits to select one of the many sources on CompLN inputs. Refer to Pimux diagram for details. | EALLOW | Go |
88h | ADCDACLOOPBACK | Enabble loopback from DAC to ADCs | Go | |
8Eh | LOCK | Lock Register | EALLOW | Go |
102h | AGPIOCTRLA | AGPIO Control Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 15-7 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WOnce | W Once | Write Write once |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
INTERNALTESTCTL is shown in Figure 15-6 and described in Table 15-8.
Return to the Summary Table.
INTERNALTEST Node Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TESTSEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | Write Key. Writes to this register must include the value 0xA5A5 in the KEY bit field to take effect. Otherwise the register will remain as it was prior to the write attempt. Reads will return a 0. Reset type: SYSRSn |
15-8 | RESERVED | R-0 | 0h | Reserved |
7-5 | RESERVED | R/W | 0h | Reserved |
4-0 | TESTSEL | R/W | 0h | Test Select. This bit field defines which internal node, if any, is selected to come out on the INTERNALTEST node connected to the ADC. 00000 No internal connection 00001 VDDCORE 00010 VREFLOA 00100 CDAC1H 00101 CDAC1L 00110 CDAC2H 00111 CDAC2L 01000 CDAC3H 01001 CDAC3L 01010 CDAC4H 01011 CDAC4L 01100 VDDA 01101 VSSA 10010 VREFLOC 10011 ENZ_CALIB_GAIN_3P3V (VREFHI*0.9V is brought to the pins for the gain calibration) Others Reserved Reset type: SYSRSn |
CONFIGLOCK is shown in Figure 15-7 and described in Table 15-9.
Return to the Summary Table.
Lock Register for all the config registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | AGPIOCTRL | RESERVED | RESERVED | RESERVED | ||
R-0-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R-0 | 0h | Reserved |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | AGPIOCTRL | R/WSonce | 0h | Locks all AGPIOCTRL Register. Setting this bit will disable any future writes to this reigster. This bit can only be cleared by a reset. Reset type: SYSRSn |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | RESERVED | R/WSonce | 0h | Reserved |
0 | RESERVED | R/WSonce | 0h | Reserved |
TSNSCTL is shown in Figure 15-8 and described in Table 15-10.
Return to the Summary Table.
Temperature Sensor Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | RESERVED | R-0 | 0h | Reserved |
0 | ENABLE | R/W | 0h | Temperature Sensor Enable. This bit enables the temperature sensor output to the ADC. 0 Disabled 1 Enabled Reset type: SYSRSn |
ANAREFCTL is shown in Figure 15-9 and described in Table 15-11.
Return to the Summary Table.
Analog Reference Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | ANAREF2P5SEL | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | ANAREFSEL | ||||
R-0-0h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R-0 | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | ANAREF2P5SEL | R/W | 0h | Analog reference A 2.5V source select. In internal reference mode, this bit selects which voltage the internal reference buffer drives onto the VREFHI pin. The buffer can drive either 1.65V onto the pin, resulting in a reference range of 0 to 3.3V, or the buffer can drive 2.5V onto the pin, resulting in a reference range of 0 to 2.5V. If switching between these two modes, the user must allow adequate time for the external capacitor to charge to the new voltage before using the ADC or buffered DAC. 0 Internal 1.65V reference mode (3.3V reference range) 1 Internal 2.5V reference mode (2.5V reference range) Reset type: XRSn |
7-3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R/W | 1h | Reserved |
1 | RESERVED | R/W | 1h | Reserved |
0 | ANAREFSEL | R/W | 1h | Analog reference mode select. This bit selects whether the VREFHI pin uses internal reference mode (the device drives a voltage onto the VREFHI pin) or external reference mode (the system is expected to drive a voltage into the VREFHI pin). 0 Internal reference mode 1 External reference mode Reset type: XRSn |
VMONCTL is shown in Figure 15-10 and described in Table 15-12.
Return to the Summary Table.
Voltage Monitor Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BORLVMONDIS | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R-0 | 0h | Reserved |
8 | BORLVMONDIS | R/W | 0h | BORL disable on VDDIO. 0 BORL is enabled on VDDIO, i.e BOR circuit will be triggered if VDDIO goes lower than the lower BOR threshold of VDDIO. 1 BORL is disabled on VDDIO, i.e BOR circuit will not be triggered if VDDIO goes lower than the lower BOR threshold of VDDIO. Reset type: SYSRSn |
7-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
CMPHPMXSEL is shown in Figure 15-11 and described in Table 15-13.
Return to the Summary Table.
Bits to select one of the many sources on CompHP inputs. Refer to Pimux diagram for details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | CMP4HPMXSEL | CMP3HPMXSEL | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMP3HPMXSEL | CMP2HPMXSEL | CMP1HPMXSEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R-0 | 0h | Reserved |
21-19 | RESERVED | R/W | 0h | Reserved |
18-16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R-0 | 0h | Reserved |
14-12 | RESERVED | R/W | 0h | Reserved |
11-9 | CMP4HPMXSEL | R/W | 0h | CMP4HPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
8-6 | CMP3HPMXSEL | R/W | 0h | CMP3HPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
5-3 | CMP2HPMXSEL | R/W | 0h | CMP2HPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
2-0 | CMP1HPMXSEL | R/W | 0h | CMP1HPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
CMPLPMXSEL is shown in Figure 15-12 and described in Table 15-14.
Return to the Summary Table.
Bits to select one of the many sources on CompLP inputs. Refer to Pimux diagram for details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | CMP4LPMXSEL | CMP3LPMXSEL | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMP3LPMXSEL | CMP2LPMXSEL | CMP1LPMXSEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R-0 | 0h | Reserved |
21-19 | RESERVED | R/W | 0h | Reserved |
18-16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R-0 | 0h | Reserved |
14-12 | RESERVED | R/W | 0h | Reserved |
11-9 | CMP4LPMXSEL | R/W | 0h | CMP4LPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
8-6 | CMP3LPMXSEL | R/W | 0h | CMP3LPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
5-3 | CMP2LPMXSEL | R/W | 0h | CMP2LPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
2-0 | CMP1LPMXSEL | R/W | 0h | CMP1LPMXSEL bits, Refer to the Analog Subsystem chapter Note: Only values 0 to 5 are valid, rest are reserved Reset type: XRSn |
CMPHNMXSEL is shown in Figure 15-13 and described in Table 15-15.
Return to the Summary Table.
Bits to select one of the many sources on CompHN inputs. Refer to Pimux diagram for details.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CMP4HNMXSEL | CMP3HNMXSEL | CMP2HNMXSEL | CMP1HNMXSEL |
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R-0 | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | CMP4HNMXSEL | R/W | 0h | CMP4HNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
2 | CMP3HNMXSEL | R/W | 0h | CMP3HNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
1 | CMP2HNMXSEL | R/W | 0h | CMP2HNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
0 | CMP1HNMXSEL | R/W | 0h | CMP1HNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
CMPLNMXSEL is shown in Figure 15-14 and described in Table 15-16.
Return to the Summary Table.
Bits to select one of the many sources on CompLN inputs. Refer to Pimux diagram for details.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CMP4LNMXSEL | CMP3LNMXSEL | CMP2LNMXSEL | CMP1LNMXSEL |
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R-0 | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | CMP4LNMXSEL | R/W | 0h | CMP4LNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
2 | CMP3LNMXSEL | R/W | 0h | CMP3LNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
1 | CMP2LNMXSEL | R/W | 0h | CMP2LNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
0 | CMP1LNMXSEL | R/W | 0h | CMP1LNMXSEL bits, Refer to the Analog Subsystem chapter Reset type: XRSn |
ADCDACLOOPBACK is shown in Figure 15-15 and described in Table 15-17.
Return to the Summary Table.
Enabble loopback from DAC to ADCs
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENLB2ADCC | ENLB2ADCB | ENLB2ADCA | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | Write Key. Writes to this register must include the value 0xA5A5 in the KEY bit field to take effect. Otherwise the register will remain as it was prior to the write attempt. Reads will return a 0. Reset type: XRSn |
15-3 | RESERVED | R-0 | 0h | Reserved |
2 | ENLB2ADCC | R/W | 0h | 1 Loops back CMPSS1 DACL output to ADCC. 0 Loop back is broken. Note: Setting this bit to 1, will override the CHSEL specification for the ADC. ADC would sample CMPSS1 DACL output irrespective of the value of CHSEL. Reset type: XRSn |
1 | ENLB2ADCB | R/W | 0h | 1 Loops back CMPSS1 DACL output to ADCB. 0 Loop back is broken. Note: Setting this bit to 1, will override the CHSEL specification for the ADC. ADC would sample CMPSS1 DACL output irrespective of the value of CHSEL. Reset type: XRSn |
0 | ENLB2ADCA | R/W | 0h | 1 Loops back CMPSS1 DACL output to ADCA. 0 Loop back is broken. Note: Setting this bit to 1, will override the CHSEL specification for the ADC. ADC would sample CMPSS1 DACL output irrespective of the value of CHSEL. Reset type: XRSn |
LOCK is shown in Figure 15-16 and described in Table 15-18.
Return to the Summary Table.
Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VREGCTL | CMPLNMXSEL | |||||
R-0-0h | R/WSonce-0h | R/WSonce-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPHNMXSEL | CMPLPMXSEL | CMPHPMXSEL | RESERVED | RESERVED | VMONCTL | ANAREFCTL | TSNSCTL |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R-0 | 0h | Reserved |
9 | VREGCTL | R/WSonce | 0h | VREGCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
8 | CMPLNMXSEL | R/WSonce | 0h | CMPLNMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
7 | CMPHNMXSEL | R/WSonce | 0h | CMPHNMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
6 | CMPLPMXSEL | R/WSonce | 0h | CMPLPMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
5 | CMPHPMXSEL | R/WSonce | 0h | CMPHPMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | VMONCTL | R/WSonce | 0h | VMONCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
1 | ANAREFCTL | R/WSonce | 0h | ANAREFCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
0 | TSNSCTL | R/WSonce | 0h | TSNSCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
AGPIOCTRLA is shown in Figure 15-17 and described in Table 15-19.
Return to the Summary Table.
AGPIO Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO21 | GPIO20 | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | GPIO21 | R/W | 0h | One time configuration for GPIO21 to decide whether AGPIO PAD or Analog PAD is pinned out Reset type: XRSn |
20 | GPIO20 | R/W | 0h | One time configuration for GPIO20 to decide whether AGPIO PAD or Analog PAD is pinned out Reset type: XRSn |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |