SPRUIW9C October   2021  – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Simulate External Reset (SIMRESET.XRS)
      4. 3.4.4  Power-On Reset (POR)
      5. 3.4.5  Brown-Out-Reset (BOR)
      6. 3.4.6  Debugger Reset (SYSRS)
      7. 3.4.7  Simulate CPU Reset (SIMRESET.CPU1RS)
      8. 3.4.8  Watchdog Reset (WDRS)
      9. 3.4.9  Hardware BIST Reset (HWBISTRS)
      10. 3.4.10 NMI Watchdog Reset (NMIWDRS)
      11. 3.4.11 DCSM Safe Code Copy Reset (SCCRESET)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
        1. 3.5.5.1 PIE Interrupt Priority
          1. 3.5.5.1.1 Channel Priority
          2. 3.5.5.1.2 Group Priority
      6. 3.5.6 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection
        2. 3.6.3.2 RAM Uncorrectable Error
        3. 3.6.3.3 Flash Uncorrectable ECC Error
        4. 3.6.3.4 CPU HWBIST Error
        5. 3.6.3.5 Software-Forced Error
      4. 3.6.4 CRC Fail
      5. 3.6.5 ERAD NMI
      6. 3.6.6 Illegal Instruction Trap (ITRAP)
      7. 3.6.7 Error Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 Auxiliary Clock Input (AUXCLKIN)
        4. 3.7.1.4 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CAN Bit Clock
        6. 3.7.3.6 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
        1. 3.7.7.1 X1/X2 Precondition Circuit
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
      5. 3.10.5 Flash Power-down Considerations
    11. 3.11 Memory Controller Module
      1. 3.11.1  Dedicated RAM (Mx RAM)
      2. 3.11.2  Local Shared RAM (LSx RAM)
      3. 3.11.3  Global Shared RAM (GSx RAM)
      4. 3.11.4  CLA-CPU Message RAM
      5. 3.11.5  CLA-DMA Message RAM
      6. 3.11.6  Access Arbitration
      7. 3.11.7  Access Protection
        1. 3.11.7.1 CPU Fetch Protection
        2. 3.11.7.2 CPU Write Protection
        3. 3.11.7.3 CPU Read Protection
        4. 3.11.7.4 CLA Fetch Protection
        5. 3.11.7.5 CLA Read Protection
        6. 3.11.7.6 CLA Write Protection
        7. 3.11.7.7 HIC Write Protection
        8. 3.11.7.8 DMA Write Protection
      8. 3.11.8  Memory Error Detection and Correction, and Error Handling
        1. 3.11.8.1 Error Detection and Correction
        2. 3.11.8.2 Error Handling
      9. 3.11.9  Application Test Hooks for Error Detection and Correction
      10. 3.11.10 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 Live Firmware Update
      1. 3.13.1 LFU Background
      2. 3.13.2 LFU Switchover Steps
      3. 3.13.3 Device Features Supporting LFU
        1. 3.13.3.1 Multi-Bank Flash
        2. 3.13.3.2 PIE Vector Table Swap
        3. 3.13.3.3 LS0/LS1 RAM Memory Swap
          1. 3.13.3.3.1 Applicability to CLA LFU
      4. 3.13.4 LFU Switchover
      5. 3.13.5 LFU Resources
    14. 3.14 System Control Register Configuration Restrictions
    15. 3.15 Software
      1. 3.15.1 INTERRUPT Examples
        1. 3.15.1.1 External Interrupts (ExternalInterrupt)
        2. 3.15.1.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.15.1.3 CPU Timer Interrupt Software Prioritization
        4. 3.15.1.4 EPWM Real-Time Interrupt
      2. 3.15.2 SYSCTL Examples
        1. 3.15.2.1 Missing clock detection (MCD)
        2. 3.15.2.2 XCLKOUT (External Clock Output) Configuration
      3. 3.15.3 TIMER Examples
        1. 3.15.3.1 CPU Timers
        2. 3.15.3.2 CPU Timers
      4. 3.15.4 LPM Examples
        1. 3.15.4.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
        2. 3.15.4.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
        3. 3.15.4.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
        4. 3.15.4.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
        5. 3.15.4.5 Low Power Modes: Halt Mode and Wakeup using GPIO
        6. 3.15.4.6 Low Power Modes: Halt Mode and Wakeup
      5. 3.15.5 MEMCFG Examples
        1. 3.15.5.1 Correctable & Uncorrectable Memory Error Handling
      6. 3.15.6 WATCHDOG Examples
        1. 3.15.6.1 Watchdog
    16. 3.16 System Control Registers
      1. 3.16.1  SYSCTRL Base Address Table
      2. 3.16.2  ACCESS_PROTECTION_REGS Registers
      3. 3.16.3  CLK_CFG_REGS Registers
      4. 3.16.4  CPU_SYS_REGS Registers
      5. 3.16.5  CPUTIMER_REGS Registers
      6. 3.16.6  DEV_CFG_REGS Registers
      7. 3.16.7  DMA_CLA_SRC_SEL_REGS Registers
      8. 3.16.8  MEM_CFG_REGS Registers
      9. 3.16.9  MEMORY_ERROR_REGS Registers
      10. 3.16.10 NMI_INTRUPT_REGS Registers
      11. 3.16.11 PERIPH_AC_REGS Registers
      12. 3.16.12 PIE_CTRL_REGS Registers
      13. 3.16.13 SYNC_SOC_REGS Registers
      14. 3.16.14 SYS_STATUS_REGS Registers
      15. 3.16.15 TEST_ERROR_REGS Registers
      16. 3.16.16 UID_REGS Registers
      17. 3.16.17 WD_REGS Registers
      18. 3.16.18 XINT_REGS Registers
      19. 3.16.19 LFU_REGS Registers
      20. 3.16.20 Register to Driverlib Function Mapping
        1. 3.16.20.1 CPUTIMER Registers to Driverlib Functions
        2. 3.16.20.2 DCSM Registers to Driverlib Functions
        3. 3.16.20.3 MEMCFG Registers to Driverlib Functions
        4. 3.16.20.4 NMI Registers to Driverlib Functions
        5. 3.16.20.5 PIE Registers to Driverlib Functions
        6. 3.16.20.6 SYSCTL Registers to Driverlib Functions
        7. 3.16.20.7 WWD Registers to Driverlib Functions
        8. 3.16.20.8 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1  Introduction
    2. 4.2  ROM Related Collateral
    3. 4.3  Device Boot Sequence
    4. 4.4  Device Boot Modes
      1. 4.4.1 Default Boot Modes
      2. 4.4.2 Custom Boot Modes
    5. 4.5  Device Boot Configurations
      1. 4.5.1 Configuring Boot Mode Pins
      2. 4.5.2 Configuring Boot Mode Table Options
      3. 4.5.3 Boot Mode Example Use Cases
        1. 4.5.3.1 Zero Boot Mode Select Pins
        2. 4.5.3.2 One Boot Mode Select Pin
        3. 4.5.3.3 Three Boot Mode Select Pins
    6. 4.6  Device Boot Flow Diagrams
      1. 4.6.1 Boot Flow
      2. 4.6.2 Emulation Boot Flow
      3. 4.6.3 Standalone Boot Flow
    7. 4.7  Device Reset and Exception Handling
      1. 4.7.1 Reset Causes and Handling
      2. 4.7.2 Exceptions and Interrupts Handling
    8. 4.8  Boot ROM Description
      1. 4.8.1  Boot ROM Configuration Registers
        1. 4.8.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.8.2  Entry Points
      3. 4.8.3  Wait Points
      4. 4.8.4  Secure Flash Boot
        1. 4.8.4.1 Secure Flash CPU1 Linker File Example
      5. 4.8.5  Firmware Update (FWU) Flash Boot
      6. 4.8.6  Memory Maps
        1. 4.8.6.1 Boot ROM Memory Maps
        2. 4.8.6.2 CLA Data ROM Memory Maps
        3. 4.8.6.3 Reserved RAM Memory Maps
      7. 4.8.7  ROM Tables
      8. 4.8.8  Boot Modes and Loaders
        1. 4.8.8.1 Boot Modes
          1. 4.8.8.1.1 Flash Boot
          2. 4.8.8.1.2 RAM Boot
          3. 4.8.8.1.3 Wait Boot
        2. 4.8.8.2 Bootloaders
          1. 4.8.8.2.1 SCI Boot Mode
          2. 4.8.8.2.2 SPI Boot Mode
          3. 4.8.8.2.3 I2C Boot Mode
          4. 4.8.8.2.4 Parallel Boot Mode
          5. 4.8.8.2.5 CAN Boot Mode
          6. 4.8.8.2.6 CAN-FD Boot Mode
      9. 4.8.9  GPIO Assignments
      10. 4.8.10 Secure ROM Function APIs
      11. 4.8.11 Clock Initializations
      12. 4.8.12 Boot Status Information
        1. 4.8.12.1 Booting Status
        2. 4.8.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      13. 4.8.13 ROM Version
    9. 4.9  Application Notes for Using the Bootloaders
      1. 4.9.1 Bootloader Data Stream Structure
        1. 4.9.1.1 Data Stream Structure 8-bit
      2. 4.9.2 The C2000 Hex Utility
        1. 4.9.2.1 HEX2000.exe Command Syntax
    10. 4.10 Software
      1. 4.10.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Password Lock
      5. 5.2.5 JTAGLOCK
      6. 5.2.6 Link Pointer and Zone Select
      7. 5.2.7 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Module Controller (FMC)
    4. 6.4  Flash and OTP Memory Power-Down Modes and Wakeup
    5. 6.5  Active Grace Period
    6. 6.6  Flash and OTP Memory Performance
    7. 6.7  Flash Read Interface
      1. 6.7.1 C28x-FMC Flash Read Interface
        1. 6.7.1.1 Standard Read Mode
        2. 6.7.1.2 Prefetch Mode
          1. 6.7.1.2.1 Data Cache
    8. 6.8  Flash Erase and Program
      1. 6.8.1 Erase
      2. 6.8.2 Program
      3. 6.8.3 Verify
    9. 6.9  Error Correction Code (ECC) Protection
      1. 6.9.1 Single-Bit Data Error
      2. 6.9.2 Uncorrectable Error
      3. 6.9.3 SECDED Logic Correctness Check
    10. 6.10 Reserved Locations Within Flash and OTP Memory
    11. 6.11 Migrating an Application from RAM to Flash
    12. 6.12 Procedure to Change the Flash Control Registers
    13. 6.13 Software
      1. 6.13.1 FLASH Examples
        1. 6.13.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        2. 6.13.1.2 Flash ECC Test Mode
        3. 6.13.1.3 Boot Source Code
        4. 6.13.1.4 Erase Source Code
        5. 6.13.1.5 Live DFU Command Functionality
        6. 6.13.1.6 Verify Source Code
        7. 6.13.1.7 SCI Boot Mode Routines
        8. 6.13.1.8 Flash Programming Solution using SCI
    14. 6.14 Flash Registers
      1. 6.14.1 FLASH Base Address Table
      2. 6.14.2 FLASH_CTRL_REGS Registers
      3. 6.14.3 FLASH_ECC_REGS Registers
      4. 6.14.4 FLASH Registers to Driverlib Functions
  9. 7 Control Law Accelerator (CLA)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 CLA Related Collateral
      3. 7.1.3 Block Diagram
    2. 7.2 CLA Interface
      1. 7.2.1 CLA Memory
      2. 7.2.2 CLA Memory Bus
      3. 7.2.3 Shared Peripherals and EALLOW Protection
      4. 7.2.4 CLA Tasks and Interrupt Vectors
    3. 7.3 CLA and CPU Arbitration
      1. 7.3.1 CLA Message RAM
      2. 7.3.2 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 7.4 CLA Configuration and Debug
      1. 7.4.1 Building a CLA Application
      2. 7.4.2 Typical CLA Initialization Sequence
      3. 7.4.3 Debugging CLA Code
        1. 7.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 7.4.3.2 Breakpoint Support (MDEBUGSTOP)
      4. 7.4.4 CLA Illegal Opcode Behavior
      5. 7.4.5 Resetting the CLA
    5. 7.5 Pipeline
      1. 7.5.1 Pipeline Overview
      2. 7.5.2 CLA Pipeline Alignment
        1. 7.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       362
        3. 7.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       364
        5. 7.5.2.3 ADC Early Interrupt to CLA Response
      3. 7.5.3 Parallel Instructions
        1. 7.5.3.1 Math Operation with Parallel Load
        2. 7.5.3.2 Multiply with Parallel Add
      4. 7.5.4 CLA Task Execution Latency
    6. 7.6 Software
      1. 7.6.1 CLA Examples
        1. 7.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 7.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        3. 7.6.1.3 CLA background nesting task
        4. 7.6.1.4 Controlling PWM output using CLA
        5. 7.6.1.5 Just-in-time ADC sampling with CLA
        6. 7.6.1.6 Optimal offloading of control algorithms to CLA
        7. 7.6.1.7 Handling shared resources across C28x and CLA
    7. 7.7 Instruction Set
      1. 7.7.1 Instruction Descriptions
      2. 7.7.2 Addressing Modes and Encoding
      3. 7.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest {, CNDF}
        11.       MCCNDD 16BitDest {, CNDF}
        12.       MCMP32 MRa, MRb
        13.       MCMPF32 MRa, MRb
        14.       MCMPF32 MRa, #16FHi
        15.       MDEBUGSTOP
        16.       MEALLOW
        17.       MEDIS
        18.       MEINVF32 MRa, MRb
        19.       MEISQRTF32 MRa, MRb
        20.       MF32TOI16 MRa, MRb
        21.       MF32TOI16R MRa, MRb
        22.       MF32TOI32 MRa, MRb
        23.       MF32TOUI16 MRa, MRb
        24.       MF32TOUI16R MRa, MRb
        25.       MF32TOUI32 MRa, MRb
        26.       MFRACF32 MRa, MRb
        27.       MI16TOF32 MRa, MRb
        28.       MI16TOF32 MRa, mem16
        29.       MI32TOF32 MRa, mem32
        30.       MI32TOF32 MRa, MRb
        31.       MLSL32 MRa, #SHIFT
        32.       MLSR32 MRa, #SHIFT
        33.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        34.       MMAXF32 MRa, MRb
        35.       MMAXF32 MRa, #16FHi
        36.       MMINF32 MRa, MRb
        37.       MMINF32 MRa, #16FHi
        38.       MMOV16 MARx, MRa, #16I
        39.       MMOV16 MARx, mem16
        40.       MMOV16 mem16, MARx
        41.       MMOV16 mem16, MRa
        42.       MMOV32 mem32, MRa
        43.       MMOV32 mem32, MSTF
        44.       MMOV32 MRa, mem32 {, CNDF}
        45.       MMOV32 MRa, MRb {, CNDF}
        46.       MMOV32 MSTF, mem32
        47.       MMOVD32 MRa, mem32
        48.       MMOVF32 MRa, #32F
        49.       MMOVI16 MARx, #16I
        50.       MMOVI32 MRa, #32FHex
        51.       MMOVIZ MRa, #16FHi
        52.       MMOVZ16 MRa, mem16
        53.       MMOVXI MRa, #16FLoHex
        54.       MMPYF32 MRa, MRb, MRc
        55.       MMPYF32 MRa, #16FHi, MRb
        56.       MMPYF32 MRa, MRb, #16FHi
        57.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        58.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        59.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        60.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        61.       MNEGF32 MRa, MRb{, CNDF}
        62.       MNOP
        63.       MOR32 MRa, MRb, MRc
        64.       MRCNDD {CNDF}
        65.       MSETFLG FLAG, VALUE
        66.       MSTOP
        67.       MSUB32 MRa, MRb, MRc
        68.       MSUBF32 MRa, MRb, MRc
        69.       MSUBF32 MRa, #16FHi, MRb
        70.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        71.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        72.       MSWAPF MRa, MRb {, CNDF}
        73.       MTESTTF CNDF
        74.       MUI16TOF32 MRa, mem16
        75.       MUI16TOF32 MRa, MRb
        76.       MUI32TOF32 MRa, mem32
        77.       MUI32TOF32 MRa, MRb
        78.       MXOR32 MRa, MRb, MRc
    8. 7.8 CLA Registers
      1. 7.8.1 CLA Base Address Table
      2. 7.8.2 CLA_ONLY_REGS Registers
      3. 7.8.3 CLA_SOFTINT_REGS Registers
      4. 7.8.4 CLA_REGS Registers
      5. 7.8.5 CLA Registers to Driverlib Functions
  10. 8 Dual-Clock Comparator (DCC)
    1. 8.1 Introduction
      1. 8.1.1 Features
      2. 8.1.2 Block Diagram
    2. 8.2 Module Operation
      1. 8.2.1 Configuring DCC Counters
      2. 8.2.2 Single-Shot Measurement Mode
      3. 8.2.3 Continuous Monitoring Mode
      4. 8.2.4 Error Conditions
    3. 8.3 Interrupts
    4. 8.4 Software
      1. 8.4.1 DCC Examples
        1. 8.4.1.1 DCC Single shot Clock verification
        2. 8.4.1.2 DCC Single shot Clock measurement
        3. 8.4.1.3 DCC Continuous clock monitoring
        4. 8.4.1.4 DCC Continuous clock monitoring
        5. 8.4.1.5 DCC Detection of clock failure
    5. 8.5 DCC Registers
      1. 8.5.1 DCC Base Address Table
      2. 8.5.2 DCC_REGS Registers
      3. 8.5.3 DCC Registers to Driverlib Functions
  11. 9 Background CRC-32 (BGCRC)
    1. 9.1 Introduction
      1. 9.1.1 BGCRC Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Block Diagram
      4. 9.1.4 Memory Wait States and Memory Map
    2. 9.2 Functional Description
      1. 9.2.1 Data Read Unit
      2. 9.2.2 CRC-32 Compute Unit
      3. 9.2.3 CRC Notification Unit
        1. 9.2.3.1 CPU Interrupt, CLA Task and NMI
      4. 9.2.4 Operating Modes
        1. 9.2.4.1 CRC Mode
        2. 9.2.4.2 Scrub Mode
      5. 9.2.5 BGCRC Watchdog
      6. 9.2.6 Hardware and Software Faults Protection
    3. 9.3 Application of the BGCRC
      1. 9.3.1 Software Configuration
      2. 9.3.2 Decision on Error Response Severity
      3. 9.3.3 Decision of Controller for CLA_CRC
      4. 9.3.4 Execution of Time Critical Code from Wait-Stated Memories
      5. 9.3.5 BGCRC Execution
      6. 9.3.6 Debug/Error Response for BGCRC Errors
      7. 9.3.7 BGCRC Golden CRC-32 Value Computation
    4. 9.4 Software
      1. 9.4.1 BGCRC Examples
        1. 9.4.1.1 BGCRC CPU Interrupt Example
        2. 9.4.1.2 BGCRC Example with Watchdog and Lock
        3. 9.4.1.3 CLA-BGCRC Example in CRC mode
        4. 9.4.1.4 CLA-BGCRC Example in Scrub Mode
    5. 9.5 BGCRC Registers
      1. 9.5.1 BGCRC Base Address Table
      2. 9.5.2 BGCRC_REGS Registers
      3. 9.5.3 BGCRC Registers to Driverlib Functions
  12. 10General-Purpose Input/Output (GPIO)
    1. 10.1  Introduction
      1. 10.1.1 GPIO Related Collateral
    2. 10.2  Configuration Overview
    3. 10.3  Digital Inputs on ADC Pins (AIOs)
    4. 10.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 10.5  Digital General-Purpose I/O Control
    6. 10.6  Input Qualification
      1. 10.6.1 No Synchronization (Asynchronous Input)
      2. 10.6.2 Synchronization to SYSCLKOUT Only
      3. 10.6.3 Qualification Using a Sampling Window
    7. 10.7  GPIO and Peripheral Muxing
      1. 10.7.1 GPIO Muxing
      2. 10.7.2 Peripheral Muxing
    8. 10.8  Internal Pullup Configuration Requirements
    9. 10.9  Software
      1. 10.9.1 GPIO Examples
        1. 10.9.1.1 Device GPIO Setup
        2. 10.9.1.2 Device GPIO Toggle
        3. 10.9.1.3 Device GPIO Interrupt
        4. 10.9.1.4 External Interrupt (XINT)
      2. 10.9.2 LED Examples
    10. 10.10 GPIO Registers
      1. 10.10.1 GPIO Base Address Table
      2. 10.10.2 GPIO_CTRL_REGS Registers
      3. 10.10.3 GPIO_DATA_REGS Registers
      4. 10.10.4 GPIO_DATA_READ_REGS Registers
      5. 10.10.5 GPIO Registers to Driverlib Functions
  13. 11Crossbar (X-BAR)
    1. 11.1 Input X-BAR and CLB Input X-BAR
      1. 11.1.1 CLB Input X-BAR
    2. 11.2 ePWM, CLB, and GPIO Output X-BAR
      1. 11.2.1 ePWM X-BAR
        1. 11.2.1.1 ePWM X-BAR Architecture
      2. 11.2.2 CLB X-BAR
        1. 11.2.2.1 CLB X-BAR Architecture
      3. 11.2.3 GPIO Output X-BAR
        1. 11.2.3.1 GPIO Output X-BAR Architecture
      4. 11.2.4 CLB Output X-BAR
        1. 11.2.4.1 CLB Output X-BAR Architecture
      5. 11.2.5 X-BAR Flags
    3. 11.3 XBAR Registers
      1. 11.3.1 XBAR Base Address Table
      2. 11.3.2 INPUT_XBAR_REGS Registers
      3. 11.3.3 XBAR_REGS Registers
      4. 11.3.4 EPWM_XBAR_REGS Registers
      5. 11.3.5 CLB_XBAR_REGS Registers
      6. 11.3.6 OUTPUT_XBAR_REGS Registers
      7. 11.3.7 Register to Driverlib Function Mapping
        1. 11.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 11.3.7.2 XBAR Registers to Driverlib Functions
        3. 11.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 11.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 11.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  14. 12Direct Memory Access (DMA)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Architecture
      1. 12.2.1 Peripheral Interrupt Event Trigger Sources
      2. 12.2.2 DMA Bus
    3. 12.3 Address Pointer and Transfer Control
    4. 12.4 Pipeline Timing and Throughput
    5. 12.5 CPU and CLA Arbitration
    6. 12.6 Channel Priority
      1. 12.6.1 Round-Robin Mode
      2. 12.6.2 Channel 1 High-Priority Mode
    7. 12.7 Overrun Detection Feature
    8. 12.8 Software
      1. 12.8.1 DMA Examples
        1. 12.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 12.8.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 12.9 DMA Registers
      1. 12.9.1 DMA Base Address Table
      2. 12.9.2 DMA_REGS Registers
      3. 12.9.3 DMA_CH_REGS Registers
      4. 12.9.4 DMA Registers to Driverlib Functions
  15. 13Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 13.1 Introduction
      1. 13.1.1 ERAD Related Collateral
    2. 13.2 Enhanced Bus Comparator Unit
      1. 13.2.1 Enhanced Bus Comparator Unit Operations
      2. 13.2.2 Event Masking and Exporting
    3. 13.3 System Event Counter Unit
      1. 13.3.1 System Event Counter Modes
        1. 13.3.1.1 Counting Active Levels Versus Edges
        2. 13.3.1.2 Max Mode
        3. 13.3.1.3 Cumulative Mode
        4. 13.3.1.4 Input Signal Selection
      2. 13.3.2 Reset on Event
      3. 13.3.3 Operation Conditions
    4. 13.4 ERAD Ownership, Initialization and Reset
    5. 13.5 ERAD Programming Sequence
      1. 13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 13.5.2 Timer and Counter Programming Sequence
    6. 13.6 Cyclic Redundancy Check Unit
      1. 13.6.1 CRC Unit Qualifier
      2. 13.6.2 CRC Unit Programming Sequence
    7. 13.7 Program Counter Trace
      1. 13.7.1 Functional Block Diagram
      2. 13.7.2 Trace Qualification Modes
        1. 13.7.2.1 Trace Qualifier Input Signals
      3. 13.7.3 Trace Memory
      4. 13.7.4 Trace Input Signal Conditioning
      5. 13.7.5 PC Trace Software Operation
      6. 13.7.6 Trace Operation in Debug Mode
    8. 13.8 Software
      1. 13.8.1 ERAD Examples
        1. 13.8.1.1  ERAD Profiling Interrupts
        2. 13.8.1.2  ERAD Profile Function
        3. 13.8.1.3  ERAD Profile Function
        4. 13.8.1.4  ERAD HWBP Monitor Program Counter
        5. 13.8.1.5  ERAD HWBP Monitor Program Counter
        6. 13.8.1.6  ERAD Profile Function
        7. 13.8.1.7  ERAD HWBP Stack Overflow Detection
        8. 13.8.1.8  ERAD HWBP Stack Overflow Detection
        9. 13.8.1.9  ERAD Stack Overflow
        10. 13.8.1.10 ERAD Profile Interrupts CLA
        11. 13.8.1.11 ERAD Profiling Interrupts
        12. 13.8.1.12 ERAD Profiling Interrupts
        13. 13.8.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 13.8.1.14 ERAD INTERRUPT ORDER
        15. 13.8.1.15 ERAD AND CLB
        16. 13.8.1.16 ERAD PWM PROTECTION
    9. 13.9 ERAD Registers
      1. 13.9.1 ERAD Base Address Table
      2. 13.9.2 ERAD_GLOBAL_REGS Registers
      3. 13.9.3 ERAD_HWBP_REGS Registers
      4. 13.9.4 ERAD_COUNTER_REGS Registers
      5. 13.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 13.9.6 ERAD_CRC_REGS Registers
      7. 13.9.7 ERAD Registers to Driverlib Functions
  16. 14Host Interface Controller (HIC)
    1. 14.1 Introduction
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
      3. 14.1.3 HIC Related Collateral
    2. 14.2 Functional Description
      1. 14.2.1 Memory Map
      2. 14.2.2 Connections
        1. 14.2.2.1 Functions of the Connections
      3. 14.2.3 Interrupts and Triggers
    3. 14.3 Operation
      1. 14.3.1 Mailbox Access Mode Overview
        1. 14.3.1.1 Mailbox Access Mode Operation
        2. 14.3.1.2 Configuring HIC Registers With External Host
        3. 14.3.1.3 Mailbox Access Mode Read/Write
      2. 14.3.2 Direct Access Mode Overview
        1. 14.3.2.1 Direct Access Mode Operation
        2. 14.3.2.2 Direct Access Mode Read/Write
      3. 14.3.3 Controlling Reads and Writes
        1. 14.3.3.1 Single-Pin Read/Write Mode (nOE/RnW Pin)
        2. 14.3.3.2 Dual-Pin Read/Write Mode (nOE and nWE Pins)
      4. 14.3.4 Data Lines, Data Width, Data Packing and Unpacking
      5. 14.3.5 Address Translation
      6. 14.3.6 Access Errors
      7. 14.3.7 Security
      8. 14.3.8 HIC Usage
    4. 14.4 Usage Scenarious for Reduced Number of Pins
    5. 14.5 Software
      1. 14.5.1 HIC Examples
        1. 14.5.1.1 HIC 16-bit Memory Access Example
        2. 14.5.1.2 HIC 8-bit Memory Access Example
        3. 14.5.1.3 HIC 16-bit Memory Access FSI Example
    6. 14.6 HIC Registers
      1. 14.6.1 HIC Base Address Table
      2. 14.6.2 HIC_CFG_REGS Registers
      3. 14.6.3 HIC Registers to Driverlib Functions
  17. 15Analog Subsystem
    1. 15.1 Introduction
      1. 15.1.1 Features
      2. 15.1.2 Block Diagram
    2. 15.2 Optimizing Power-Up Time
    3. 15.3 Digital Inputs on ADC Pins (AIOs)
    4. 15.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5 Analog Pins and Internal Connections
    6. 15.6 Analog Subsystem Registers
      1. 15.6.1 ASBSYS Base Address Table
      2. 15.6.2 ANALOG_SUBSYS_REGS Registers
      3. 15.6.3 ASYSCTL Registers to Driverlib Functions
  18. 16Analog-to-Digital Converter (ADC)
    1. 16.1  Introduction
      1. 16.1.1 ADC Related Collateral
      2. 16.1.2 Features
      3. 16.1.3 Block Diagram
    2. 16.2  ADC Configurability
      1. 16.2.1 Clock Configuration
      2. 16.2.2 Resolution
      3. 16.2.3 Voltage Reference
        1. 16.2.3.1 External Reference Mode
        2. 16.2.3.2 Internal Reference Mode
        3. 16.2.3.3 Selecting Reference Mode
      4. 16.2.4 Signal Mode
      5. 16.2.5 Expected Conversion Results
      6. 16.2.6 Interpreting Conversion Results
    3. 16.3  SOC Principle of Operation
      1. 16.3.1 SOC Configuration
      2. 16.3.2 Trigger Operation
      3. 16.3.3 ADC Acquisition (Sample and Hold) Window
      4. 16.3.4 ADC Input Models
      5. 16.3.5 Channel Selection
    4. 16.4  SOC Configuration Examples
      1. 16.4.1 Single Conversion from ePWM Trigger
      2. 16.4.2 Oversampled Conversion from ePWM Trigger
      3. 16.4.3 Multiple Conversions from CPU Timer Trigger
      4. 16.4.4 Software Triggering of SOCs
    5. 16.5  ADC Conversion Priority
    6. 16.6  Burst Mode
      1. 16.6.1 Burst Mode Example
      2. 16.6.2 Burst Mode Priority Example
    7. 16.7  EOC and Interrupt Operation
      1. 16.7.1 Interrupt Overflow
      2. 16.7.2 Continue to Interrupt Mode
      3. 16.7.3 Early Interrupt Configuration Mode
    8. 16.8  Post-Processing Blocks
      1. 16.8.1 PPB Offset Correction
      2. 16.8.2 PPB Error Calculation
      3. 16.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 16.8.4 PPB Sample Delay Capture
    9. 16.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 16.9.1 Implementation
      2. 16.9.2 Detecting an Open Input Pin
      3. 16.9.3 Detecting a Shorted Input Pin
    10. 16.10 Power-Up Sequence
    11. 16.11 ADC Calibration
      1. 16.11.1 ADC Zero Offset Calibration
    12. 16.12 ADC Timings
      1. 16.12.1 ADC Timing Diagrams
    13. 16.13 Additional Information
      1. 16.13.1 Ensuring Synchronous Operation
        1. 16.13.1.1 Basic Synchronous Operation
        2. 16.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 16.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 16.13.1.4 Non-overlapping Conversions
      2. 16.13.2 Choosing an Acquisition Window Duration
      3. 16.13.3 Achieving Simultaneous Sampling
      4. 16.13.4 Result Register Mapping
      5. 16.13.5 Internal Temperature Sensor
      6. 16.13.6 Designing an External Reference Circuit
      7. 16.13.7 ADC-DAC Loopback Testing
      8. 16.13.8 Internal Test Mode
      9. 16.13.9 ADC Gain and Offset Calibration
    14. 16.14 Software
      1. 16.14.1 ADC Examples
        1. 16.14.1.1  ADC Software Triggering
        2. 16.14.1.2  ADC ePWM Triggering
        3. 16.14.1.3  ADC Temperature Sensor Conversion
        4. 16.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 16.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 16.14.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        7. 16.14.1.7  ADC PPB Offset (adc_ppb_offset)
        8. 16.14.1.8  ADC PPB Limits (adc_ppb_limits)
        9. 16.14.1.9  ADC PPB Delay Capture (adc_ppb_delay)
        10. 16.14.1.10 ADC ePWM Triggering Multiple SOC
        11. 16.14.1.11 ADC Burst Mode
        12. 16.14.1.12 ADC Burst Mode Oversampling
        13. 16.14.1.13 ADC SOC Oversampling
        14. 16.14.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip)
        15. 16.14.1.15 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 16.15 ADC Registers
      1. 16.15.1 ADC Base Address Table
      2. 16.15.2 ADC_RESULT_REGS Registers
      3. 16.15.3 ADC_REGS Registers
      4. 16.15.4 ADC Registers to Driverlib Functions
  19. 17Buffered Digital-to-Analog Converter (DAC)
    1. 17.1 Introduction
      1. 17.1.1 DAC Related Collateral
      2. 17.1.2 Features
      3. 17.1.3 Block Diagram
    2. 17.2 Using the DAC
      1. 17.2.1 Initialization Sequence
      2. 17.2.2 DAC Offset Adjustment
      3. 17.2.3 EPWMSYNCPER Signal
    3. 17.3 Lock Registers
    4. 17.4 Software
      1. 17.4.1 DAC Examples
        1. 17.4.1.1 Buffered DAC Enable
        2. 17.4.1.2 Buffered DAC Random
        3. 17.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 17.5 DAC Registers
      1. 17.5.1 DAC Base Address Table
      2. 17.5.2 DAC_REGS Registers
      3. 17.5.3 DAC Registers to Driverlib Functions
  20. 18Comparator Subsystem (CMPSS)
    1. 18.1 Introduction
      1. 18.1.1 CMPSS Related Collateral
      2. 18.1.2 Features
      3. 18.1.3 Block Diagram
    2. 18.2 Comparator
    3. 18.3 Reference DAC
    4. 18.4 Ramp Generator
      1. 18.4.1 Ramp Generator Overview
      2. 18.4.2 Ramp Generator Behavior
      3. 18.4.3 Ramp Generator Behavior at Corner Cases
    5. 18.5 Digital Filter
      1. 18.5.1 Filter Initialization Sequence
    6. 18.6 Using the CMPSS
      1. 18.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 18.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 18.6.3 Calibrating the CMPSS
      4. 18.6.4 Enabling and Disabling the CMPSS Clock
    7. 18.7 Software
      1. 18.7.1 CMPSS Examples
        1. 18.7.1.1 CMPSS Asynchronous Trip
        2. 18.7.1.2 CMPSS Digital Filter Configuration
    8. 18.8 CMPSS Registers
      1. 18.8.1 CMPSS Base Address Table
      2. 18.8.2 CMPSS_REGS Registers
      3. 18.8.3 CMPSS Registers to Driverlib Functions
  21. 19Sigma Delta Filter Module (SDFM)
    1. 19.1  Introduction
      1. 19.1.1 SDFM Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Block Diagram
    2. 19.2  Configuring Device Pins
    3. 19.3  Input Qualification
    4. 19.4  Input Control Unit
    5. 19.5  SDFM Clock Control
    6. 19.6  Sinc Filter
      1. 19.6.1 Data Rate and Latency of the Sinc Filter
    7. 19.7  Data (Primary) Filter Unit
      1. 19.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 19.7.2 Data FIFO
      3. 19.7.3 SDSYNC Event
    8. 19.8  Comparator (Secondary) Filter Unit
      1. 19.8.1 Higher Threshold (HLT) Comparators
      2. 19.8.2 Lower Threshold (LLT) Comparators
      3. 19.8.3 Digital Filter
    9. 19.9  Theoretical SDFM Filter Output
    10. 19.10 Interrupt Unit
      1. 19.10.1 SDFM (SDyERR) Interrupt Sources
      2. 19.10.2 Data Ready (DRINT) Interrupt Sources
    11. 19.11 Software
      1. 19.11.1 SDFM Examples
        1. 19.11.1.1 SDFM Filter Sync CPU
        2. 19.11.1.2 SDFM Filter Sync CLA
        3. 19.11.1.3 SDFM Filter Sync DMA
        4. 19.11.1.4 SDFM PWM Sync
        5. 19.11.1.5 SDFM Type 1 Filter FIFO
        6. 19.11.1.6 SDFM Filter Sync CLA
    12. 19.12 SDFM Registers
      1. 19.12.1 SDFM Base Address Table
      2. 19.12.2 SDFM_REGS Registers
      3. 19.12.3 SDFM Registers to Driverlib Functions
  22. 20Enhanced Pulse Width Modulator (ePWM)
    1. 20.1  Introduction
      1. 20.1.1 EPWM Related Collateral
      2. 20.1.2 Submodule Overview
    2. 20.2  Configuring Device Pins
    3. 20.3  ePWM Modules Overview
    4. 20.4  Time-Base (TB) Submodule
      1. 20.4.1 Purpose of the Time-Base Submodule
      2. 20.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 20.4.3 Calculating PWM Period and Frequency
        1. 20.4.3.1 Time-Base Period Shadow Register
        2. 20.4.3.2 Time-Base Clock Synchronization
        3. 20.4.3.3 Time-Base Counter Synchronization
        4. 20.4.3.4 ePWM SYNC Selection
      4. 20.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 20.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 20.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 20.4.7 Global Load
        1. 20.4.7.1 Global Load Pulse Pre-Scalar
        2. 20.4.7.2 One-Shot Load Mode
        3. 20.4.7.3 One-Shot Sync Mode
    5. 20.5  Counter-Compare (CC) Submodule
      1. 20.5.1 Purpose of the Counter-Compare Submodule
      2. 20.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 20.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 20.5.4 Count Mode Timing Waveforms
    6. 20.6  Action-Qualifier (AQ) Submodule
      1. 20.6.1 Purpose of the Action-Qualifier Submodule
      2. 20.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 20.6.3 Action-Qualifier Event Priority
      4. 20.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 20.6.5 Configuration Requirements for Common Waveforms
    7. 20.7  Dead-Band Generator (DB) Submodule
      1. 20.7.1 Purpose of the Dead-Band Submodule
      2. 20.7.2 Dead-band Submodule Additional Operating Modes
      3. 20.7.3 Operational Highlights for the Dead-Band Submodule
    8. 20.8  PWM Chopper (PC) Submodule
      1. 20.8.1 Purpose of the PWM Chopper Submodule
      2. 20.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 20.8.3 Waveforms
        1. 20.8.3.1 One-Shot Pulse
        2. 20.8.3.2 Duty Cycle Control
    9. 20.9  Trip-Zone (TZ) Submodule
      1. 20.9.1 Purpose of the Trip-Zone Submodule
      2. 20.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 20.9.2.1 Trip-Zone Configurations
      3. 20.9.3 Generating Trip Event Interrupts
    10. 20.10 Event-Trigger (ET) Submodule
      1. 20.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 20.11 Digital Compare (DC) Submodule
      1. 20.11.1 Purpose of the Digital Compare Submodule
      2. 20.11.2 Enhanced Trip Action Using CMPSS
      3. 20.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 20.11.4 Operation Highlights of the Digital Compare Submodule
        1. 20.11.4.1 Digital Compare Events
        2. 20.11.4.2 Event Filtering
        3. 20.11.4.3 Valley Switching
    12. 20.12 ePWM Crossbar (X-BAR)
    13. 20.13 Applications to Power Topologies
      1. 20.13.1  Overview of Multiple Modules
      2. 20.13.2  Key Configuration Capabilities
      3. 20.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 20.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 20.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 20.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 20.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 20.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 20.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 20.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 20.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 20.14 Register Lock Protection
    15. 20.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 20.15.1 Operational Description of HRPWM
        1. 20.15.1.1 Controlling the HRPWM Capabilities
        2. 20.15.1.2 HRPWM Source Clock
        3. 20.15.1.3 Configuring the HRPWM
        4. 20.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 20.15.1.5 Principle of Operation
          1. 20.15.1.5.1 Edge Positioning
          2. 20.15.1.5.2 Scaling Considerations
          3. 20.15.1.5.3 Duty Cycle Range Limitation
          4. 20.15.1.5.4 High-Resolution Period
            1. 20.15.1.5.4.1 High-Resolution Period Configuration
        6. 20.15.1.6 Deadband High-Resolution Operation
        7. 20.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 20.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 20.15.1.8.1 #Defines for HRPWM Header Files
          2. 20.15.1.8.2 Implementing a Simple Buck Converter
            1. 20.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 20.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 20.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 20.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 20.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 20.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 20.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 20.15.2.2 Software Usage
          1. 20.15.2.2.1 A Sample of How to Add "Include" Files
          2.        963
          3. 20.15.2.2.2 Declaring an Element
          4.        965
          5. 20.15.2.2.3 Initializing With a Scale Factor Value
          6.        967
          7. 20.15.2.2.4 SFO Function Calls
    16. 20.16 Software
      1. 20.16.1 EPWM Examples
        1. 20.16.1.1  ePWM Trip Zone
        2. 20.16.1.2  ePWM Up Down Count Action Qualifier
        3. 20.16.1.3  ePWM Synchronization
        4. 20.16.1.4  ePWM Digital Compare
        5. 20.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 20.16.1.6  ePWM Valley Switching
        7. 20.16.1.7  ePWM Digital Compare Edge Filter
        8. 20.16.1.8  ePWM Deadband
        9. 20.16.1.9  ePWM DMA
        10. 20.16.1.10 ePWM Chopper
        11. 20.16.1.11 EPWM Configure Signal
        12. 20.16.1.12 Realization of Monoshot mode
        13. 20.16.1.13 EPWM Action Qualifier (epwm_up_aq)
      2. 20.16.2 HRPWM Examples
        1. 20.16.2.1 HRPWM Duty Control with SFO
        2. 20.16.2.2 HRPWM Slider
        3. 20.16.2.3 HRPWM Period Control
        4. 20.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 20.16.2.5 HRPWM Slider Test
        6. 20.16.2.6 HRPWM Duty Up Count
        7. 20.16.2.7 HRPWM Period Up-Down Count
    17. 20.17 ePWM Registers
      1. 20.17.1 EPWM Base Address Table
      2. 20.17.2 EPWM_REGS Registers
      3. 20.17.3 Register to Driverlib Function Mapping
        1. 20.17.3.1 EPWM Registers to Driverlib Functions
        2. 20.17.3.2 HRPWM Registers to Driverlib Functions
  23. 21Enhanced Capture (eCAP)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 ECAP Related Collateral
    2. 21.2 Description
    3. 21.3 Configuring Device Pins for the eCAP
    4. 21.4 Capture and APWM Operating Mode
    5. 21.5 Capture Mode Description
      1. 21.5.1  Event Prescaler
      2. 21.5.2  Edge Polarity Select and Qualifier
      3. 21.5.3  Continuous/One-Shot Control
      4. 21.5.4  32-Bit Counter and Phase Control
      5. 21.5.5  CAP1-CAP4 Registers
      6. 21.5.6  eCAP Synchronization
        1. 21.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 21.5.7  Interrupt Control
      8. 21.5.8  DMA Interrupt
      9. 21.5.9  Shadow Load and Lockout Control
      10. 21.5.10 APWM Mode Operation
    6. 21.6 Application of the eCAP Module
      1. 21.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 21.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 21.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 21.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 21.7 Application of the APWM Mode
      1. 21.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 21.8 Software
      1. 21.8.1 ECAP Examples
        1. 21.8.1.1 eCAP APWM Example
        2. 21.8.1.2 eCAP Capture PWM Example
        3. 21.8.1.3 eCAP APWM Phase-shift Example
        4. 21.8.1.4 eCAP Software Sync Example
    9. 21.9 eCAP Registers
      1. 21.9.1 ECAP Base Address Table
      2. 21.9.2 ECAP_REGS Registers
      3. 21.9.3 ECAP Registers to Driverlib Functions
  24. 22High Resolution Capture (HRCAP)
    1. 22.1 Introduction
      1. 22.1.1 HRCAP Related Collateral
      2. 22.1.2 Features
      3. 22.1.3 Description
    2. 22.2 Operational Details
      1. 22.2.1 HRCAP Clocking
      2. 22.2.2 HRCAP Initialization Sequence
      3. 22.2.3 HRCAP Interrupts
      4. 22.2.4 HRCAP Calibration
        1. 22.2.4.1 Applying the Scale Factor
    3. 22.3 Known Exceptions
    4. 22.4 Software
      1. 22.4.1 HRCAP Examples
        1. 22.4.1.1 HRCAP Capture and Calibration Example
    5. 22.5 HRCAP Registers
      1. 22.5.1 HRCAP Base Address Table
      2. 22.5.2 HRCAP_REGS Registers
      3. 22.5.3 HRCAP Registers to Driverlib Functions
  25. 23Enhanced Quadrature Encoder Pulse (eQEP)
    1. 23.1  Introduction
      1. 23.1.1 EQEP Related Collateral
    2. 23.2  Configuring Device Pins
    3. 23.3  Description
      1. 23.3.1 EQEP Inputs
      2. 23.3.2 Functional Description
      3. 23.3.3 eQEP Memory Map
    4. 23.4  Quadrature Decoder Unit (QDU)
      1. 23.4.1 Position Counter Input Modes
        1. 23.4.1.1 Quadrature Count Mode
        2. 23.4.1.2 Direction-Count Mode
        3. 23.4.1.3 Up-Count Mode
        4. 23.4.1.4 Down-Count Mode
      2. 23.4.2 eQEP Input Polarity Selection
      3. 23.4.3 Position-Compare Sync Output
    5. 23.5  Position Counter and Control Unit (PCCU)
      1. 23.5.1 Position Counter Operating Modes
        1. 23.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 23.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 23.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 23.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 23.5.2 Position Counter Latch
        1. 23.5.2.1 Index Event Latch
        2. 23.5.2.2 Strobe Event Latch
      3. 23.5.3 Position Counter Initialization
      4. 23.5.4 eQEP Position-compare Unit
    6. 23.6  eQEP Edge Capture Unit
    7. 23.7  eQEP Watchdog
    8. 23.8  eQEP Unit Timer Base
    9. 23.9  QMA Module
      1. 23.9.1 Modes of Operation
        1. 23.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 23.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 23.9.2 Interrupt and Error Generation
    10. 23.10 eQEP Interrupt Structure
    11. 23.11 Software
      1. 23.11.1 EQEP Examples
        1. 23.11.1.1 Frequency Measurement Using eQEP
        2. 23.11.1.2 Position and Speed Measurement Using eQEP
        3. 23.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 23.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 23.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 23.12 eQEP Registers
      1. 23.12.1 EQEP Base Address Table
      2. 23.12.2 EQEP_REGS Registers
      3. 23.12.3 EQEP Registers to Driverlib Functions
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Introduction
      1. 24.1.1 Features
      2. 24.1.2 SPI Related Collateral
      3. 24.1.3 Block Diagram
    2. 24.2 System-Level Integration
      1. 24.2.1 SPI Module Signals
      2. 24.2.2 Configuring Device Pins
        1. 24.2.2.1 GPIOs Required for High-Speed Mode
      3. 24.2.3 SPI Interrupts
      4. 24.2.4 DMA Support
    3. 24.3 SPI Operation
      1. 24.3.1 Introduction to Operation
      2. 24.3.2 Master Mode
      3. 24.3.3 Slave Mode
      4. 24.3.4 Data Format
        1. 24.3.4.1 Transmission of Bit from SPIRXBUF
      5. 24.3.5 Baud Rate Selection
        1. 24.3.5.1 Baud Rate Determination
        2. 24.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 24.3.6 SPI Clocking Schemes
      7. 24.3.7 SPI FIFO Description
      8. 24.3.8 SPI DMA Transfers
        1. 24.3.8.1 Transmitting Data Using SPI with DMA
        2. 24.3.8.2 Receiving Data Using SPI with DMA
    4. 24.4 Programming Procedure
      1. 24.4.1 Initialization Upon Reset
      2. 24.4.2 Configuring the SPI
      3. 24.4.3 Data Transfer Example
    5. 24.5 Software
      1. 24.5.1 SPI Examples
        1. 24.5.1.1 SPI Digital Loopback
        2. 24.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 24.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 24.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 24.5.1.5 SPI Digital Loopback with DMA
        6. 24.5.1.6 SPI EEPROM
        7. 24.5.1.7 SPI DMA EEPROM
    6. 24.6 SPI Registers
      1. 24.6.1 SPI Base Address Table
      2. 24.6.2 SPI_REGS Registers
      3. 24.6.3 SPI Registers to Driverlib Functions
  27. 25Serial Communications Interface (SCI)
    1. 25.1  Introduction
      1. 25.1.1 Features
      2. 25.1.2 SCI Related Collateral
      3. 25.1.3 Block Diagram
    2. 25.2  Architecture
    3. 25.3  SCI Module Signal Summary
    4. 25.4  Configuring Device Pins
    5. 25.5  Multiprocessor and Asynchronous Communication Modes
    6. 25.6  SCI Programmable Data Format
    7. 25.7  SCI Multiprocessor Communication
      1. 25.7.1 Recognizing the Address Byte
      2. 25.7.2 Controlling the SCI TX and RX Features
      3. 25.7.3 Receipt Sequence
    8. 25.8  Idle-Line Multiprocessor Mode
      1. 25.8.1 Idle-Line Mode Steps
      2. 25.8.2 Block Start Signal
      3. 25.8.3 Wake-Up Temporary (WUT) Flag
        1. 25.8.3.1 Sending a Block Start Signal
      4. 25.8.4 Receiver Operation
    9. 25.9  Address-Bit Multiprocessor Mode
      1. 25.9.1 Sending an Address
    10. 25.10 SCI Communication Format
      1. 25.10.1 Receiver Signals in Communication Modes
      2. 25.10.2 Transmitter Signals in Communication Modes
    11. 25.11 SCI Port Interrupts
      1. 25.11.1 Break Detect
    12. 25.12 SCI Baud Rate Calculations
    13. 25.13 SCI Enhanced Features
      1. 25.13.1 SCI FIFO Description
      2. 25.13.2 SCI Auto-Baud
      3. 25.13.3 Autobaud-Detect Sequence
    14. 25.14 Software
      1. 25.14.1 SCI Examples
        1. 25.14.1.1 Tune Baud Rate via UART Example
        2. 25.14.1.2 SCI FIFO Digital Loop Back
        3. 25.14.1.3 SCI Digital Loop Back with Interrupts
        4. 25.14.1.4 SCI Echoback
        5. 25.14.1.5 stdout redirect example
    15. 25.15 SCI Registers
      1. 25.15.1 SCI Base Address Table
      2. 25.15.2 SCI_REGS Registers
      3. 25.15.3 SCI Registers to Driverlib Functions
  28. 26Inter-Integrated Circuit Module (I2C)
    1. 26.1 Introduction
      1. 26.1.1 I2C Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Features Not Supported
      4. 26.1.4 Functional Overview
      5. 26.1.5 Clock Generation
      6. 26.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 26.1.6.1 Formula for the Master Clock Period
    2. 26.2 Configuring Device Pins
    3. 26.3 I2C Module Operational Details
      1. 26.3.1  Input and Output Voltage Levels
      2. 26.3.2  Selecting Pullup Resistors
      3. 26.3.3  Data Validity
      4. 26.3.4  Operating Modes
      5. 26.3.5  I2C Module START and STOP Conditions
      6. 26.3.6  Non-repeat Mode versus Repeat Mode
      7. 26.3.7  Serial Data Formats
        1. 26.3.7.1 7-Bit Addressing Format
        2. 26.3.7.2 10-Bit Addressing Format
        3. 26.3.7.3 Free Data Format
        4. 26.3.7.4 Using a Repeated START Condition
      8. 26.3.8  Clock Synchronization
      9. 26.3.9  Arbitration
      10. 26.3.10 Digital Loopback Mode
      11. 26.3.11 NACK Bit Generation
    4. 26.4 Interrupt Requests Generated by the I2C Module
      1. 26.4.1 Basic I2C Interrupt Requests
      2. 26.4.2 I2C FIFO Interrupts
    5. 26.5 Resetting or Disabling the I2C Module
    6. 26.6 Software
      1. 26.6.1 I2C Examples
        1. 26.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 26.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 26.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 26.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 26.6.1.5 I2C EEPROM
        6. 26.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 26.6.1.7 I2C EEPROM
        8. 26.6.1.8 I2C controller target communication using FIFO interrupts
        9. 26.6.1.9 I2C EEPROM
    7. 26.7 I2C Registers
      1. 26.7.1 I2C Base Address Table
      2. 26.7.2 I2C_REGS Registers
      3. 26.7.3 I2C Registers to Driverlib Functions
  29. 27Power Management Bus Module (PMBus)
    1. 27.1 Introduction
      1. 27.1.1 PMBUS Related Collateral
      2. 27.1.2 Features
      3. 27.1.3 Block Diagram
    2. 27.2 Configuring Device Pins
    3. 27.3 Slave Mode Operation
      1. 27.3.1 Configuration
      2. 27.3.2 Message Handling
        1. 27.3.2.1  Quick Command
        2. 27.3.2.2  Send Byte
        3. 27.3.2.3  Receive Byte
        4. 27.3.2.4  Write Byte and Write Word
        5. 27.3.2.5  Read Byte and Read Word
        6. 27.3.2.6  Process Call
        7. 27.3.2.7  Block Write
        8. 27.3.2.8  Block Read
        9. 27.3.2.9  Block Write-Block Read Process Call
        10. 27.3.2.10 Alert Response
        11. 27.3.2.11 Extended Command
        12. 27.3.2.12 Group Command
    4. 27.4 Master Mode Operation
      1. 27.4.1 Configuration
      2. 27.4.2 Message Handling
        1. 27.4.2.1  Quick Command
        2. 27.4.2.2  Send Byte
        3. 27.4.2.3  Receive Byte
        4. 27.4.2.4  Write Byte and Write Word
        5. 27.4.2.5  Read Byte and Read Word
        6. 27.4.2.6  Process Call
        7. 27.4.2.7  Block Write
        8. 27.4.2.8  Block Read
        9. 27.4.2.9  Block Write-Block Read Process Call
        10. 27.4.2.10 Alert Response
        11. 27.4.2.11 Extended Command
        12. 27.4.2.12 Group Command
    5. 27.5 PMBus Registers
      1. 27.5.1 PMBUS Base Address Table
      2. 27.5.2 PMBUS_REGS Registers
      3. 27.5.3 PMBUS Registers to Driverlib Functions
  30. 28Controller Area Network (CAN)
    1. 28.1  Introduction
      1. 28.1.1 DCAN Related Collateral
      2. 28.1.2 Features
      3. 28.1.3 Block Diagram
        1. 28.1.3.1 CAN Core
        2. 28.1.3.2 Message Handler
        3. 28.1.3.3 Message RAM
        4. 28.1.3.4 Registers and Message Object Access (IFx)
    2. 28.2  Functional Description
      1. 28.2.1 Configuring Device Pins
      2. 28.2.2 Address/Data Bus Bridge
    3. 28.3  Operating Modes
      1. 28.3.1 Initialization
      2. 28.3.2 CAN Message Transfer (Normal Operation)
        1. 28.3.2.1 Disabled Automatic Retransmission
        2. 28.3.2.2 Auto-Bus-On
      3. 28.3.3 Test Modes
        1. 28.3.3.1 Silent Mode
        2. 28.3.3.2 Loopback Mode
        3. 28.3.3.3 External Loopback Mode
        4. 28.3.3.4 Loopback Combined with Silent Mode
    4. 28.4  Multiple Clock Source
    5. 28.5  Interrupt Functionality
      1. 28.5.1 Message Object Interrupts
      2. 28.5.2 Status Change Interrupts
      3. 28.5.3 Error Interrupts
      4. 28.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 28.5.5 Interrupt Topologies
    6. 28.6  DMA Functionality
    7. 28.7  Parity Check Mechanism
      1. 28.7.1 Behavior on Parity Error
    8. 28.8  Debug Mode
    9. 28.9  Module Initialization
    10. 28.10 Configuration of Message Objects
      1. 28.10.1 Configuration of a Transmit Object for Data Frames
      2. 28.10.2 Configuration of a Transmit Object for Remote Frames
      3. 28.10.3 Configuration of a Single Receive Object for Data Frames
      4. 28.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 28.10.5 Configuration of a FIFO Buffer
    11. 28.11 Message Handling
      1. 28.11.1  Message Handler Overview
      2. 28.11.2  Receive/Transmit Priority
      3. 28.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 28.11.4  Updating a Transmit Object
      5. 28.11.5  Changing a Transmit Object
      6. 28.11.6  Acceptance Filtering of Received Messages
      7. 28.11.7  Reception of Data Frames
      8. 28.11.8  Reception of Remote Frames
      9. 28.11.9  Reading Received Messages
      10. 28.11.10 Requesting New Data for a Receive Object
      11. 28.11.11 Storing Received Messages in FIFO Buffers
      12. 28.11.12 Reading from a FIFO Buffer
    12. 28.12 CAN Bit Timing
      1. 28.12.1 Bit Time and Bit Rate
        1. 28.12.1.1 Synchronization Segment
        2. 28.12.1.2 Propagation Time Segment
        3. 28.12.1.3 Phase Buffer Segments and Synchronization
        4. 28.12.1.4 Oscillator Tolerance Range
      2. 28.12.2 Configuration of the CAN Bit Timing
        1. 28.12.2.1 Calculation of the Bit Timing Parameters
        2. 28.12.2.2 Example for Bit Timing at High Baudrate
        3. 28.12.2.3 Example for Bit Timing at Low Baudrate
    13. 28.13 Message Interface Register Sets
      1. 28.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 28.13.2 Message Interface Register Set 3 (IF3)
    14. 28.14 Message RAM
      1. 28.14.1 Structure of Message Objects
      2. 28.14.2 Addressing Message Objects in RAM
      3. 28.14.3 Message RAM Representation in Debug Mode
    15. 28.15 Software
      1. 28.15.1 CAN Examples
        1. 28.15.1.1 CAN External Loopback
        2. 28.15.1.2 CAN External Loopback with Interrupts
        3. 28.15.1.3 CAN External Loopback with DMA
        4. 28.15.1.4 CAN Transmit and Receive Configurations
        5. 28.15.1.5 CAN Error Generation Example
        6. 28.15.1.6 CAN Remote Request Loopback
        7. 28.15.1.7 CAN example that illustrates the usage of Mask registers
    16. 28.16 CAN Registers
      1. 28.16.1 CAN Base Address Table
      2. 28.16.2 CAN_REGS Registers
      3. 28.16.3 CAN Registers to Driverlib Functions
  31. 29Modular Controller Area Network (MCAN)
    1. 29.1 MCAN Introduction
      1. 29.1.1 MCAN Related Collateral
      2. 29.1.2 MCAN Features
    2. 29.2 MCAN Environment
    3. 29.3 CAN Network Basics
    4. 29.4 MCAN Integration
    5. 29.5 MCAN Functional Description
      1. 29.5.1  Module Clocking Requirements
      2. 29.5.2  Interrupt Requests
      3. 29.5.3  Operating Modes
        1. 29.5.3.1 Software Initialization
        2. 29.5.3.2 Normal Operation
        3. 29.5.3.3 CAN FD Operation
      4. 29.5.4  Transmitter Delay Compensation
        1. 29.5.4.1 Description
        2. 29.5.4.2 Transmitter Delay Compensation Measurement
      5. 29.5.5  Restricted Operation Mode
      6. 29.5.6  Bus Monitoring Mode
      7. 29.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 29.5.7.1 Frame Transmission in DAR Mode
      8. 29.5.8  Clock Stop Mode
        1. 29.5.8.1 Suspend Mode
        2. 29.5.8.2 Wakeup Request
      9. 29.5.9  Test Modes
        1. 29.5.9.1 External Loop Back Mode
        2. 29.5.9.2 Internal Loop Back Mode
      10. 29.5.10 Timestamp Generation
        1. 29.5.10.1 External Timestamp Counter
      11. 29.5.11 Timeout Counter
      12. 29.5.12 Safety
        1. 29.5.12.1 ECC Wrapper
        2. 29.5.12.2 ECC Aggregator
          1. 29.5.12.2.1 ECC Aggregator Overview
          2. 29.5.12.2.2 ECC Aggregator Registers
        3. 29.5.12.3 Reads to ECC Control and Status Registers
        4. 29.5.12.4 ECC Interrupts
      13. 29.5.13 Rx Handling
        1. 29.5.13.1 Acceptance Filtering
          1. 29.5.13.1.1 Range Filter
          2. 29.5.13.1.2 Filter for Specific IDs
          3. 29.5.13.1.3 Classic Bit Mask Filter
          4. 29.5.13.1.4 Standard Message ID Filtering
          5. 29.5.13.1.5 Extended Message ID Filtering
        2. 29.5.13.2 Rx FIFOs
          1. 29.5.13.2.1 Rx FIFO Blocking Mode
          2. 29.5.13.2.2 Rx FIFO Overwrite Mode
        3. 29.5.13.3 Dedicated Rx Buffers
          1. 29.5.13.3.1 Rx Buffer Handling
      14. 29.5.14 Tx Handling
        1. 29.5.14.1 Transmit Pause
        2. 29.5.14.2 Dedicated Tx Buffers
        3. 29.5.14.3 Tx FIFO
        4. 29.5.14.4 Tx Queue
        5. 29.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 29.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 29.5.14.7 Transmit Cancellation
        8. 29.5.14.8 Tx Event Handling
      15. 29.5.15 FIFO Acknowledge Handling
      16. 29.5.16 Message RAM
        1. 29.5.16.1 Message RAM Configuration
        2. 29.5.16.2 Rx Buffer and FIFO Element
        3. 29.5.16.3 Tx Buffer Element
        4. 29.5.16.4 Tx Event FIFO Element
        5. 29.5.16.5 Standard Message ID Filter Element
        6. 29.5.16.6 Extended Message ID Filter Element
    6. 29.6 Software
      1. 29.6.1 MCAN Examples
        1. 29.6.1.1  MCAN Internal Loopback with Interrupt
        2. 29.6.1.2  MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
        3. 29.6.1.3  MCAN receive using Rx Buffer
        4. 29.6.1.4  MCAN External Reception (with mask filter) into RX-FIFO1
        5. 29.6.1.5  MCAN Classic frames transmission using Tx Buffer
        6. 29.6.1.6  MCAN External Reception (with RANGE filter) into RX-FIFO1
        7. 29.6.1.7  MCAN External Transmit using Tx Buffer
        8. 29.6.1.8  MCAN receive using Rx Buffer
        9. 29.6.1.9  MCAN Internal Loopback with Interrupt
        10. 29.6.1.10 MCAN External Transmit using Tx Buffer
    7. 29.7 MCAN Registers
      1. 29.7.1 MCAN Base Address Table
      2. 29.7.2 MCANSS_REGS Registers
      3. 29.7.3 MCAN_REGS Registers
      4. 29.7.4 MCAN_ERROR_REGS Registers
      5. 29.7.5 MCAN Registers to Driverlib Functions
  32. 30Local Interconnect Network (LIN)
    1. 30.1 Introduction
      1. 30.1.1 SCI Features
      2. 30.1.2 LIN Features
      3. 30.1.3 LIN Related Collateral
      4. 30.1.4 Block Diagram
    2. 30.2 Serial Communications Interface Module
      1. 30.2.1 SCI Communication Formats
        1. 30.2.1.1 SCI Frame Formats
        2. 30.2.1.2 SCI Asynchronous Timing Mode
        3. 30.2.1.3 SCI Baud Rate
          1. 30.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 30.2.1.4 SCI Multiprocessor Communication Modes
          1. 30.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 30.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 30.2.1.5 SCI Multibuffered Mode
      2. 30.2.2 SCI Interrupts
        1. 30.2.2.1 Transmit Interrupt
        2. 30.2.2.2 Receive Interrupt
        3. 30.2.2.3 WakeUp Interrupt
        4. 30.2.2.4 Error Interrupts
      3. 30.2.3 SCI DMA Interface
        1. 30.2.3.1 Receive DMA Requests
        2. 30.2.3.2 Transmit DMA Requests
      4. 30.2.4 SCI Configurations
        1. 30.2.4.1 Receiving Data
          1. 30.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 30.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 30.2.4.2 Transmitting Data
          1. 30.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 30.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 30.2.5 SCI Low-Power Mode
        1. 30.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 30.3 Local Interconnect Network Module
      1. 30.3.1 LIN Communication Formats
        1. 30.3.1.1  LIN Standards
        2. 30.3.1.2  Message Frame
          1. 30.3.1.2.1 Message Header
          2. 30.3.1.2.2 Response
        3. 30.3.1.3  Synchronizer
        4. 30.3.1.4  Baud Rate
          1. 30.3.1.4.1 Fractional Divider
          2. 30.3.1.4.2 Superfractional Divider
            1. 30.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 30.3.1.5  Header Generation
          1. 30.3.1.5.1 Event Triggered Frame Handling
          2. 30.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 30.3.1.6  Extended Frames Handling
        7. 30.3.1.7  Timeout Control
          1. 30.3.1.7.1 No-Response Error (NRE)
          2. 30.3.1.7.2 Bus Idle Detection
          3. 30.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 30.3.1.8  TXRX Error Detector (TED)
          1. 30.3.1.8.1 Bit Errors
          2. 30.3.1.8.2 Physical Bus Errors
          3. 30.3.1.8.3 ID Parity Errors
          4. 30.3.1.8.4 Checksum Errors
        9. 30.3.1.9  Message Filtering and Validation
        10. 30.3.1.10 Receive Buffers
        11. 30.3.1.11 Transmit Buffers
      2. 30.3.2 LIN Interrupts
      3. 30.3.3 Servicing LIN Interrupts
      4. 30.3.4 LIN DMA Interface
        1. 30.3.4.1 LIN Receive DMA Requests
        2. 30.3.4.2 LIN Transmit DMA Requests
      5. 30.3.5 LIN Configurations
        1. 30.3.5.1 Receiving Data
          1. 30.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 30.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 30.3.5.2 Transmitting Data
          1. 30.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 30.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 30.4 Low-Power Mode
      1. 30.4.1 Entering Sleep Mode
      2. 30.4.2 Wakeup
      3. 30.4.3 Wakeup Timeouts
    5. 30.5 Emulation Mode
    6. 30.6 Software
      1. 30.6.1 LIN Examples
        1. 30.6.1.1 LIN Internal Loopback with Interrupts
        2. 30.6.1.2 LIN SCI Mode Internal Loopback with Interrupts
        3. 30.6.1.3 LIN SCI MODE Internal Loopback with DMA
        4. 30.6.1.4 LIN Internal Loopback without interrupts(polled mode)
        5. 30.6.1.5 LIN Internal Loopback with Interrupts using Sysconfig
        6. 30.6.1.6 LIN Incomplete Header Detection
        7. 30.6.1.7 LIN SCI MODE (Single Buffer) Internal Loopback with DMA
        8. 30.6.1.8 LIN External Loopback without interrupts(polled mode)
    7. 30.7 SCI/LIN Registers
      1. 30.7.1 LIN Base Address Table
      2. 30.7.2 LIN_REGS Registers
      3. 30.7.3 LIN Registers to Driverlib Functions
  33. 31Fast Serial Interface (FSI)
    1. 31.1 Introduction
      1. 31.1.1 FSI Related Collateral
      2. 31.1.2 FSI Features
    2. 31.2 System-level Integration
      1. 31.2.1 CPU Interface
      2. 31.2.2 Signal Description
        1. 31.2.2.1 Configuring Device Pins
      3. 31.2.3 FSI Interrupts
        1. 31.2.3.1 Transmitter Interrupts
        2. 31.2.3.2 Receiver Interrupts
        3. 31.2.3.3 Configuring Interrupts
        4. 31.2.3.4 Handling Interrupts
      4. 31.2.4 CLA Task Triggering
      5. 31.2.5 DMA Interface
      6. 31.2.6 External Frame Trigger Mux
    3. 31.3 FSI Functional Description
      1. 31.3.1  Introduction to Operation
      2. 31.3.2  FSI Transmitter Module
        1. 31.3.2.1 Initialization
        2. 31.3.2.2 FSI_TX Clocking
        3. 31.3.2.3 Transmitting Frames
          1. 31.3.2.3.1 Software Triggered Frames
          2. 31.3.2.3.2 Externally Triggered Frames
          3. 31.3.2.3.3 Ping Frame Generation
            1. 31.3.2.3.3.1 Automatic Ping Frames
            2. 31.3.2.3.3.2 Software Triggered Ping Frame
            3. 31.3.2.3.3.3 Externally Triggered Ping Frame
          4. 31.3.2.3.4 Transmitting Frames with DMA
        4. 31.3.2.4 Transmit Buffer Management
        5. 31.3.2.5 CRC Submodule
        6. 31.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 31.3.2.7 Reset
      3. 31.3.3  FSI Receiver Module
        1. 31.3.3.1  Initialization
        2. 31.3.3.2  FSI_RX Clocking
        3. 31.3.3.3  Receiving Frames
          1. 31.3.3.3.1 Receiving Frames with DMA
        4. 31.3.3.4  Ping Frame Watchdog
        5. 31.3.3.5  Frame Watchdog
        6. 31.3.3.6  Delay Line Control
        7. 31.3.3.7  Buffer Management
        8. 31.3.3.8  CRC Submodule
        9. 31.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 31.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 31.3.3.11 FSI_RX Reset
      4. 31.3.4  Frame Format
        1. 31.3.4.1 FSI Frame Phases
        2. 31.3.4.2 Frame Types
          1. 31.3.4.2.1 Ping Frames
          2. 31.3.4.2.2 Error Frames
          3. 31.3.4.2.3 Data Frames
        3. 31.3.4.3 Multi-Lane Transmission
      5. 31.3.5  Flush Sequence
      6. 31.3.6  Internal Loopback
      7. 31.3.7  CRC Generation
      8. 31.3.8  ECC Module
      9. 31.3.9  Tag Matching
      10. 31.3.10 User Data Filtering (UDATA Matching)
      11. 31.3.11 TDM Configurations
      12. 31.3.12 FSI Trigger Generation
      13. 31.3.13 FSI-SPI Compatibility Mode
        1. 31.3.13.1 Available SPI Modes
          1. 31.3.13.1.1 FSITX as SPI Master, Transmit Only
            1. 31.3.13.1.1.1 Initialization
            2. 31.3.13.1.1.2 Operation
          2. 31.3.13.1.2 FSIRX as SPI Slave, Receive Only
            1. 31.3.13.1.2.1 Initialization
            2. 31.3.13.1.2.2 Operation
          3. 31.3.13.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Master
            1. 31.3.13.1.3.1 Initialization
            2. 31.3.13.1.3.2 Operation
    4. 31.4 FSI Programing Guide
      1. 31.4.1 Establishing the Communication Link
        1. 31.4.1.1 Establishing the Communication Link from the Master Device
        2. 31.4.1.2 Establishing the Communication Link from the Slave Device
      2. 31.4.2 Register Protection
      3. 31.4.3 Emulation Mode
    5. 31.5 Software
      1. 31.5.1 FSI Examples
        1. 31.5.1.1  FSI Loopback:CPU Control
        2. 31.5.1.2  FSI Loopback CLA control
        3. 31.5.1.3  FSI DMA frame transfers:DMA Control
        4. 31.5.1.4  FSI data transfer by external trigger
        5. 31.5.1.5  FSI data transfers upon CPU Timer event
        6. 31.5.1.6  FSI and SPI communication(fsi_ex6_spi_main_tx)
        7. 31.5.1.7  FSI and SPI communication(fsi_ex7_spi_remote_rx)
        8. 31.5.1.8  FSI P2Point Connection:Rx Side
        9. 31.5.1.9  FSI P2Point Connection:Tx Side
        10. 31.5.1.10 FSI daisy chain topology, lead device example
        11. 31.5.1.11 FSI daisy chain topology, node device example
    6. 31.6 FSI Registers
      1. 31.6.1 FSI Base Address Table
      2. 31.6.2 FSI_TX_REGS Registers
      3. 31.6.3 FSI_RX_REGS Registers
      4. 31.6.4 FSI Registers to Driverlib Functions
  34. 32Configurable Logic Block (CLB)
    1. 32.1 Introduction
      1. 32.1.1 CLB Related Collateral
    2. 32.2 Description
      1. 32.2.1 CLB Clock
    3. 32.3 CLB Input/Output Connection
      1. 32.3.1 Overview
      2. 32.3.2 CLB Input Selection
      3. 32.3.3 CLB Output Selection
      4. 32.3.4 CLB Output Signal Multiplexer
    4. 32.4 CLB Tile
      1. 32.4.1 Static Switch Block
      2. 32.4.2 Counter Block
        1. 32.4.2.1 Counter Description
        2. 32.4.2.2 Counter Operation
        3. 32.4.2.3 Serializer Mode
        4. 32.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 32.4.3 FSM Block
      4. 32.4.4 LUT4 Block
      5. 32.4.5 Output LUT Block
      6. 32.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 32.4.7 High Level Controller (HLC)
        1. 32.4.7.1 High Level Controller Events
        2. 32.4.7.2 High Level Controller Instructions
        3. 32.4.7.3 <Src> and <Dest>
        4. 32.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 32.5 CPU Interface
      1. 32.5.1 Register Description
      2. 32.5.2 Non-Memory Mapped Registers
    6. 32.6 DMA Access
    7. 32.7 CLB Data Export Through SPI RX Buffer
    8. 32.8 Software
      1. 32.8.1 CLB Examples
        1. 32.8.1.1  CLB Empty Project
        2. 32.8.1.2  CLB Combinational Logic
        3. 32.8.1.3  CLB GPIO Input Filter
        4. 32.8.1.4  CLB Auxilary PWM
        5. 32.8.1.5  CLB PWM Protection
        6. 32.8.1.6  CLB Event Window
        7. 32.8.1.7  CLB Signal Generator
        8. 32.8.1.8  CLB State Machine
        9. 32.8.1.9  CLB External Signal AND Gate
        10. 32.8.1.10 CLB Timer
        11. 32.8.1.11 CLB Timer Two States
        12. 32.8.1.12 CLB Interrupt Tag
        13. 32.8.1.13 CLB Output Intersect
        14. 32.8.1.14 CLB PUSH PULL
        15. 32.8.1.15 CLB Multi Tile
        16. 32.8.1.16 CLB Glue Logic
        17. 32.8.1.17 CLB based One-shot PWM
        18. 32.8.1.18 CLB AOC Control
        19. 32.8.1.19 CLB AOC Release Control
        20. 32.8.1.20 CLB XBARs
        21. 32.8.1.21 CLB AOC Control
        22. 32.8.1.22 CLB Serializer
        23. 32.8.1.23 CLB LFSR
        24. 32.8.1.24 CLB Lock Output Mask
        25. 32.8.1.25 CLB INPUT Pipeline Mode
        26. 32.8.1.26 CLB Clocking and PIPELINE Mode
        27. 32.8.1.27 CLB SPI Data Export
        28. 32.8.1.28 CLB SPI Data Export DMA
        29. 32.8.1.29 CLB Trip Zone Timestamp
        30. 32.8.1.30 CLB CRC
        31. 32.8.1.31 CLB TDM Serial Port
        32. 32.8.1.32 CLB LED Driver
    9. 32.9 CLB Registers
      1. 32.9.1 CLB Base Address Table
      2. 32.9.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 32.9.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 32.9.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 32.9.5 CLB Registers to Driverlib Functions
  35. 33Advanced Encryption Standard (AES) Accelerator
    1. 33.1 Introduction
      1. 33.1.1 AES Block Diagram
        1. 33.1.1.1 Interfaces
        2. 33.1.1.2 AES Subsystem
        3. 33.1.1.3 AES Wide-Bus Engine
      2. 33.1.2 AES Algorithm
    2. 33.2 AES Operating Modes
      1. 33.2.1  GCM Operation
      2. 33.2.2  CCM Operation
      3. 33.2.3  XTS Operation
      4. 33.2.4  ECB Feedback Mode
      5. 33.2.5  CBC Feedback Mode
      6. 33.2.6  CTR and ICM Feedback Modes
      7. 33.2.7  CFB Mode
      8. 33.2.8  F8 Mode
      9. 33.2.9  F9 Operation
      10. 33.2.10 CBC-MAC Operation
    3. 33.3 Extended and Combined Modes of Operations
      1. 33.3.1 GCM Protocol Operation
      2. 33.3.2 CCM Protocol Operation
      3. 33.3.3 Hardware Requests
    4. 33.4 AES Module Programming Guide
      1. 33.4.1 AES Low-Level Programming Models
        1. 33.4.1.1 Global Initialization
        2. 33.4.1.2 AES Operating Modes Configuration
        3. 33.4.1.3 AES Mode Configurations
        4. 33.4.1.4 AES Events Servicing
    5. 33.5 Software
      1. 33.5.1 AES Examples
        1. 33.5.1.1 AES ECB Encryption Example
        2. 33.5.1.2 AES ECB De-cryption Example
        3. 33.5.1.3 AES GCM Encryption Example
        4. 33.5.1.4 AES GCM Decryption Example
    6. 33.6 AES Registers
      1. 33.6.1 AES Base Address Table
      2. 33.6.2 AES_REGS Registers
      3. 33.6.3 AES_SS_REGS Registers
      4. 33.6.4 Register to Driverlib Function Mapping
        1. 33.6.4.1 AES Registers to Driverlib Functions
        2. 33.6.4.2 AES_SS Registers to Driverlib Functions
  36. 34Embedded Pattern Generator (EPG)
    1. 34.1 Introduction
      1. 34.1.1 Features
      2. 34.1.2 EPG Block Diagram
      3. 34.1.3 EPG Related Collateral
    2. 34.2 Clock Generator Modules
      1. 34.2.1 DCLK (50% duty cycle clock)
      2. 34.2.2 Clock Stop
    3. 34.3 Signal Generator Module
    4. 34.4 EPG Peripheral Signal Mux Selection
    5. 34.5 EPG Example Use Cases
      1. 34.5.1 EPG Example: Synchronous Clocks with Offset
        1. 34.5.1.1 Synchronous Clocks with Offset Register Configuration
      2. 34.5.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 34.5.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 34.5.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 34.5.3.1 Serial Data Bit Stream (MSB first) Register Configuration
    6. 34.6 EPG Interrupt
    7. 34.7 Software
      1. 34.7.1 EPG Examples
        1. 34.7.1.1 EPG Generating Synchronous Clocks
        2. 34.7.1.2 EPG Generating Two Offset Clocks
        3. 34.7.1.3 EPG Generating Two Offset Clocks With SIGGEN
        4. 34.7.1.4 EPG Generate Serial Data
        5. 34.7.1.5 EPG Generate Serial Data Shift Mode
    8. 34.8 EPG Registers
      1. 34.8.1 EPG Base Address Table
      2. 34.8.2 EPG_REGS Registers
      3. 34.8.3 EPG_MUX_REGS Registers
      4. 34.8.4 EPG Registers to Driverlib Functions
  37. 35Revision History

3.16.4 CPU_SYS_REGS Registers

Table 3-60 lists the memory-mapped registers for the CPU_SYS_REGS registers. All register offset addresses not listed in Table 3-60 should be considered as reserved locations and the register contents should not be modified.

Table 3-60 CPU_SYS_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hCPUSYSLOCK1Lock bit for CPUSYS registersEALLOWGo
2hCPUSYSLOCK2Lock bit for CPUSYS registersEALLOWGo
AhPIEVERRADDRPIE Vector Fetch Error Address registerEALLOWGo
22hPCLKCR0Peripheral Clock Gating RegistersEALLOWGo
26hPCLKCR2Peripheral Clock Gating Register - ETPWMEALLOWGo
28hPCLKCR3Peripheral Clock Gating Register - ECAPEALLOWGo
2AhPCLKCR4Peripheral Clock Gating Register - EQEPEALLOWGo
2EhPCLKCR6Peripheral Clock Gating Register - SDFMEALLOWGo
30hPCLKCR7Peripheral Clock Gating Register - SCIEALLOWGo
32hPCLKCR8Peripheral Clock Gating Register - SPIEALLOWGo
34hPCLKCR9Peripheral Clock Gating Register - I2CEALLOWGo
36hPCLKCR10Peripheral Clock Gating Register - CANEALLOWGo
3ChPCLKCR13Peripheral Clock Gating Register - ADCEALLOWGo
3EhPCLKCR14Peripheral Clock Gating Register - CMPSSEALLOWGo
42hPCLKCR16Peripheral Clock Gating Register Buf_DACEALLOWGo
44hPCLKCR17Peripheral Clock Gating Register - CLBEALLOWGo
46hPCLKCR18Peripheral Clock Gating Register - FSIEALLOWGo
48hPCLKCR19Peripheral Clock Gating Register - LINEALLOWGo
4AhPCLKCR20Peripheral Clock Gating Register - PMBUSEALLOWGo
4ChPCLKCR21Peripheral Clock Gating Register - DCCEALLOWGo
54hPCLKCR25Peripheral Clock Gating Register - HICEALLOWGo
56hPCLKCR26Peripheral Clock Gating Register - AESEALLOWGo
58hPCLKCR27Peripheral Clock Gating Register - EPGEALLOWGo
70hSIMRESETSimulated Reset RegisterGo
76hLPMCRLPM Control RegisterEALLOWGo
78hGPIOLPMSEL0GPIO LPM Wakeup select registersEALLOWGo
7AhGPIOLPMSEL1GPIO LPM Wakeup select registersEALLOWGo
7ChTMR2CLKCTLTimer2 Clock Measurement functionality control registerEALLOWGo
7EhRESCCLRReset Cause Clear RegisterGo
80hRESCReset Cause registerGo
98hMCANWAKESTATUSMCAN Wake Status RegisterGo
9AhMCANWAKESTATUSCLRMCAN Wake Status Clear RegisterGo
9ChCLKSTOPREQPeripheral Clock Stop Request RegisterGo
9EhCLKSTOPACKPeripheral Clock Stop Ackonwledge RegisterGo

Complex bit access types are encoded to fit into small table cells. Table 3-61 shows the codes that are used for access types in this section.

Table 3-61 CPU_SYS_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

3.16.4.1 CPUSYSLOCK1 Register (Offset = 0h) [Reset = 00000000h]

CPUSYSLOCK1 is shown in Figure 3-58 and described in Table 3-62.

Return to the Summary Table.

Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Figure 3-58 CPUSYSLOCK1 Register
3130292827262524
RESERVEDRESERVEDPCLKCR22PCLKCR21PCLKCR20PCLKCR19PCLKCR18PCLKCR17
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIOLPMSEL1GPIOLPMSEL0LPMCRRESERVEDPCLKCR16RESERVEDPCLKCR14PCLKCR13
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
RESERVEDRESERVEDPCLKCR10PCLKCR9PCLKCR8PCLKCR7PCLKCR6RESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
PCLKCR4PCLKCR3PCLKCR2RESERVEDPCLKCR0PIEVERRADDRRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-62 CPUSYSLOCK1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WSonce0hReserved
30RESERVEDR/WSonce0hReserved
29PCLKCR22R/WSonce0hLock bit for PCLKCR22 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

28PCLKCR21R/WSonce0hLock bit for PCLKCR21 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

27PCLKCR20R/WSonce0hLock bit for PCLKCR20 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

26PCLKCR19R/WSonce0hLock bit for PCLKCR19 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

25PCLKCR18R/WSonce0hLock bit for PCLKCR18 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

24PCLKCR17R/WSonce0hLock bit for PCLKCR17 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

23GPIOLPMSEL1R/WSonce0hLock bit for GPIOLPMSEL1 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

22GPIOLPMSEL0R/WSonce0hLock bit for GPIOLPMSEL0 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

21LPMCRR/WSonce0hLock bit for LPMCR Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

20RESERVEDR/WSonce0hReserved
19PCLKCR16R/WSonce0hLock bit for PCLKCR16 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

18RESERVEDR/WSonce0hReserved
17PCLKCR14R/WSonce0hLock bit for PCLKCR14 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

16PCLKCR13R/WSonce0hLock bit for PCLKCR13 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

15RESERVEDR/WSonce0hReserved
14RESERVEDR/WSonce0hReserved
13PCLKCR10R/WSonce0hLock bit for PCLKCR10 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

12PCLKCR9R/WSonce0hLock bit for PCLKCR9 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

11PCLKCR8R/WSonce0hLock bit for PCLKCR8 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

10PCLKCR7R/WSonce0hLock bit for PCLKCR7 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

9PCLKCR6R/WSonce0hLock bit for PCLKCR6 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

8RESERVEDR/WSonce0hReserved
7PCLKCR4R/WSonce0hLock bit for PCLKCR4 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

6PCLKCR3R/WSonce0hLock bit for PCLKCR3 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

5PCLKCR2R/WSonce0hLock bit for PCLKCR2 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

4RESERVEDR/WSonce0hReserved
3PCLKCR0R/WSonce0hLock bit for PCLKCR0 Register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: SYSRSn

2PIEVERRADDRR/WSonce0hLock bit for PIEVERRADDR Register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: SYSRSn

1RESERVEDR/WSonce0hReserved
0RESERVEDR/WSonce0hReserved

3.16.4.2 CPUSYSLOCK2 Register (Offset = 2h) [Reset = 00000000h]

CPUSYSLOCK2 is shown in Figure 3-59 and described in Table 3-63.

Return to the Summary Table.

Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Figure 3-59 CPUSYSLOCK2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPCLKCR27PCLKCR26PCLKCR25RESERVED
R-0-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-63 CPUSYSLOCK2 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3PCLKCR27R/WSonce0hLock bit for PCLKCR27 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

2PCLKCR26R/WSonce0hLock bit for PCLKCR26 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

1PCLKCR25R/WSonce0hLock bit for PCLKCR25 Register:
0: Respective register is not locked
1: Respective register is locked.


Reset type: SYSRSn

0RESERVEDR/WSonce0hReserved

3.16.4.3 PIEVERRADDR Register (Offset = Ah) [Reset = 003FFFFFh]

PIEVERRADDR is shown in Figure 3-60 and described in Table 3-64.

Return to the Summary Table.

PIE Vector Fetch Error Address register

Figure 3-60 PIEVERRADDR Register
313029282726252423222120191817161514131211109876543210
RESERVEDADDR
R-0-0hR/W-003FFFFFh
Table 3-64 PIEVERRADDR Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR-00hReserved
21-0ADDRR/W003FFFFFhThis register defines the address of the PIE Vector Fetch Error handler routine. Its the responsibility of user to initialize this register. If this register is not initialized, a default error handler at address 0x3fffbe will get executed. Refer to the Boot ROM section for more details on this register.

Reset type: XRSn

3.16.4.4 PCLKCR0 Register (Offset = 22h) [Reset = 00000038h]

PCLKCR0 is shown in Figure 3-61 and described in Table 3-65.

Return to the Summary Table.

Peripheral Clock Gating Registers

Figure 3-61 PCLKCR0 Register
3130292827262524
RESERVEDERAD
R-0-0hR/W-0h
2322212019181716
RESERVEDRESERVEDTBCLKSYNCRESERVEDHRCAL
R-0-0hR/W-0hR/W-0hR-0-0hR/W-0h
15141312111098
RESERVEDCLA1BGCRCCPUBGCRCRESERVED
R-0-0hR/W-0hR/W-0hR-0-0h
76543210
RESERVEDCPUTIMER2CPUTIMER1CPUTIMER0DMARESERVEDCLA1
R-0-0hR/W-1hR/W-1hR/W-1hR/W-0hR/W-0hR/W-0h
Table 3-65 PCLKCR0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR-00hReserved
24ERADR/W0hERAD Clock Enable Bit: When set, this enables the clock to the ERAD module
1: ERAD clock is enabled
0: ERAD clock is disabled


Reset type: SYSRSn

23-20RESERVEDR-00hReserved
19RESERVEDR/W0hReserved
18TBCLKSYNCR/W0hEPWM Time Base Clock sync: When set PWM time bases of all the PWM modules belonging to the same CPU-Subsystem (as partitioned using their CPUSEL bits) start counting

Reset type: SYSRSn

17RESERVEDR-00hReserved
16HRCALR/W0hHRCAL Clock Enable Bit: When set, this enables the clock to the HRCAL module
1: HRCAL clock is enabled
0: HRCAL clock is disabled

Reset type: SYSRSn

15RESERVEDR-00hReserved
14CLA1BGCRCR/W0hCLA1BGCRC Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on



Reset type: SYSRSn

13CPUBGCRCR/W0hCPUBGCRC Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on



Reset type: SYSRSn

12-6RESERVEDR-00hReserved
5CPUTIMER2R/W1hCPUTIMER2 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on


Reset type: SYSRSn

4CPUTIMER1R/W1hCPUTIMER1 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on


Reset type: SYSRSn

3CPUTIMER0R/W1hCPUTIMER0 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on


Reset type: SYSRSn

2DMAR/W0hDMA Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on


Reset type: SYSRSn

1RESERVEDR/W0hReserved
0CLA1R/W0hCLA1 Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.5 PCLKCR2 Register (Offset = 26h) [Reset = 00000000h]

PCLKCR2 is shown in Figure 3-62 and described in Table 3-66.

Return to the Summary Table.

Peripheral Clock Gating Register - ETPWM

Figure 3-62 PCLKCR2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-66 PCLKCR2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7EPWM8R/W0hEPWM8 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

6EPWM7R/W0hEPWM7 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

5EPWM6R/W0hEPWM6 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

4EPWM5R/W0hEPWM5 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3EPWM4R/W0hEPWM4 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

2EPWM3R/W0hEPWM3 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

1EPWM2R/W0hEPWM2 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0EPWM1R/W0hEPWM1 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.6 PCLKCR3 Register (Offset = 28h) [Reset = 00000000h]

PCLKCR3 is shown in Figure 3-63 and described in Table 3-67.

Return to the Summary Table.

Peripheral Clock Gating Register - ECAP

Figure 3-63 PCLKCR3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDECAP3ECAP2ECAP1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-67 PCLKCR3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2ECAP3R/W0hECAP3 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

1ECAP2R/W0hECAP2 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0ECAP1R/W0hECAP1 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.7 PCLKCR4 Register (Offset = 2Ah) [Reset = 00000000h]

PCLKCR4 is shown in Figure 3-64 and described in Table 3-68.

Return to the Summary Table.

Peripheral Clock Gating Register - EQEP

Figure 3-64 PCLKCR4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDEQEP2EQEP1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-68 PCLKCR4 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1EQEP2R/W0hEQEP2 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0EQEP1R/W0hEQEP1 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.8 PCLKCR6 Register (Offset = 2Eh) [Reset = 00000000h]

PCLKCR6 is shown in Figure 3-65 and described in Table 3-69.

Return to the Summary Table.

Peripheral Clock Gating Register - SDFM

Figure 3-65 PCLKCR6 Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSD2SD1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-69 PCLKCR6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1SD2R/W0hSD2 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0SD1R/W0hSD1 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.9 PCLKCR7 Register (Offset = 30h) [Reset = 00000000h]

PCLKCR7 is shown in Figure 3-66 and described in Table 3-70.

Return to the Summary Table.

Peripheral Clock Gating Register - SCI

Figure 3-66 PCLKCR7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDSCI_BSCI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-70 PCLKCR7 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1SCI_BR/W0hSCI_B Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0SCI_AR/W0hSCI_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.10 PCLKCR8 Register (Offset = 32h) [Reset = 00000000h]

PCLKCR8 is shown in Figure 3-67 and described in Table 3-71.

Return to the Summary Table.

Peripheral Clock Gating Register - SPI

Figure 3-67 PCLKCR8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDSPI_BSPI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-71 PCLKCR8 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1SPI_BR/W0hSPI_B Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0SPI_AR/W0hSPI_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.11 PCLKCR9 Register (Offset = 34h) [Reset = 00000000h]

PCLKCR9 is shown in Figure 3-68 and described in Table 3-72.

Return to the Summary Table.

Peripheral Clock Gating Register - I2C

Figure 3-68 PCLKCR9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDI2C_BI2C_A
R-0-0hR/W-0hR/W-0h
Table 3-72 PCLKCR9 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1I2C_BR/W0hI2C_B Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0I2C_AR/W0hI2C_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.12 PCLKCR10 Register (Offset = 36h) [Reset = 00000000h]

PCLKCR10 is shown in Figure 3-69 and described in Table 3-73.

Return to the Summary Table.

Peripheral Clock Gating Register - CAN

Figure 3-69 PCLKCR10 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDMCAN_ARESERVEDRESERVEDRESERVEDCAN_A
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-73 PCLKCR10 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4MCAN_AR/W0hMCAN_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0CAN_AR/W0hCAN_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.13 PCLKCR13 Register (Offset = 3Ch) [Reset = 00000000h]

PCLKCR13 is shown in Figure 3-70 and described in Table 3-74.

Return to the Summary Table.

Peripheral Clock Gating Register - ADC

Figure 3-70 PCLKCR13 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDADC_CADC_BADC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-74 PCLKCR13 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2ADC_CR/W0hADC_C Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

1ADC_BR/W0hADC_B Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0ADC_AR/W0hADC_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.14 PCLKCR14 Register (Offset = 3Eh) [Reset = 00000000h]

PCLKCR14 is shown in Figure 3-71 and described in Table 3-75.

Return to the Summary Table.

Peripheral Clock Gating Register - CMPSS

Figure 3-71 PCLKCR14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDCMPSS4CMPSS3CMPSS2CMPSS1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-75 PCLKCR14 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3CMPSS4R/W0hCMPSS4 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

2CMPSS3R/W0hCMPSS3 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

1CMPSS2R/W0hCMPSS2 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0CMPSS1R/W0hCMPSS1 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.15 PCLKCR16 Register (Offset = 42h) [Reset = 00000000h]

PCLKCR16 is shown in Figure 3-72 and described in Table 3-76.

Return to the Summary Table.

Peripheral Clock Gating Register Buf_DAC

Figure 3-72 PCLKCR16 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVEDDAC_BDAC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-76 PCLKCR16 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17DAC_BR/W0hBuffered_DAC_B Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

16DAC_AR/W0hBuffered_DAC_A Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.16.4.16 PCLKCR17 Register (Offset = 44h) [Reset = 00000000h]

PCLKCR17 is shown in Figure 3-73 and described in Table 3-77.

Return to the Summary Table.

Peripheral Clock Gating Register - CLB

Figure 3-73 PCLKCR17 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCLB4CLB3CLB2CLB1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-77 PCLKCR17 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3CLB4R/W0hCLB4 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

2CLB3R/W0hCLB3 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

1CLB2R/W0hCLB2 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0CLB1R/W0hCLB1 Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.17 PCLKCR18 Register (Offset = 46h) [Reset = 00000000h]

PCLKCR18 is shown in Figure 3-74 and described in Table 3-78.

Return to the Summary Table.

Peripheral Clock Gating Register - FSI

Figure 3-74 PCLKCR18 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDFSIRX_AFSITX_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-78 PCLKCR18 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1FSIRX_AR/W0hFSIRX_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0FSITX_AR/W0hFSITX_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.18 PCLKCR19 Register (Offset = 48h) [Reset = 00000000h]

PCLKCR19 is shown in Figure 3-75 and described in Table 3-79.

Return to the Summary Table.

Peripheral Clock Gating Register - LIN

Figure 3-75 PCLKCR19 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDLIN_BLIN_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-79 PCLKCR19 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1LIN_BR/W0hLIN_B Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0LIN_AR/W0hLIN_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.19 PCLKCR20 Register (Offset = 4Ah) [Reset = 00000000h]

PCLKCR20 is shown in Figure 3-76 and described in Table 3-80.

Return to the Summary Table.

Peripheral Clock Gating Register - PMBUS

Figure 3-76 PCLKCR20 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDPMBUS_A
R-0-0hR/W-0hR/W-0h
Table 3-80 PCLKCR20 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1RESERVEDR/W0hReserved
0PMBUS_AR/W0hPMBUS_A Clock Enable bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.20 PCLKCR21 Register (Offset = 4Ch) [Reset = 00000000h]

PCLKCR21 is shown in Figure 3-77 and described in Table 3-81.

Return to the Summary Table.

Peripheral Clock Gating Register - DCC

Figure 3-77 PCLKCR21 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDDCC1DCC0
R-0-0hR/W-0hR/W-0h
Table 3-81 PCLKCR21 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1DCC1R/W0hDCC Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

0DCC0R/W0hDCC Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.21 PCLKCR25 Register (Offset = 54h) [Reset = 00000000h]

PCLKCR25 is shown in Figure 3-78 and described in Table 3-82.

Return to the Summary Table.

Peripheral Clock Gating Register - HIC

Figure 3-78 PCLKCR25 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDHICA
R-0-0hR/W-0h
Table 3-82 PCLKCR25 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0HICAR/W0hHICA Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.22 PCLKCR26 Register (Offset = 56h) [Reset = 00000000h]

PCLKCR26 is shown in Figure 3-79 and described in Table 3-83.

Return to the Summary Table.

Peripheral Clock Gating Register - AES

Figure 3-79 PCLKCR26 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDAESA
R-0-0hR/W-0h
Table 3-83 PCLKCR26 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0AESAR/W0hAESA Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.23 PCLKCR27 Register (Offset = 58h) [Reset = 00000000h]

PCLKCR27 is shown in Figure 3-80 and described in Table 3-84.

Return to the Summary Table.

Peripheral Clock Gating Register - EPG

Figure 3-80 PCLKCR27 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDEPG1
R-0-0hR/W-0h
Table 3-84 PCLKCR27 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0EPG1R/W0hEPG1 Clock Enable Bit:

0: Module clock is gated-off
1: Module clock is turned-on

Reset type: SYSRSn

3.16.4.24 SIMRESET Register (Offset = 70h) [Reset = 00000000h]

SIMRESET is shown in Figure 3-81 and described in Table 3-85.

Return to the Summary Table.

Simulated Reset Register
Note: This register exists only on CPU1

Figure 3-81 SIMRESET Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDXRSnCPU1RSn
R-0-0hR-0/W1S-0hR-0/W1S-0h
Table 3-85 SIMRESET Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hWrite to this register succeeds only if this field is written with a value of 0xa5a5

Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored

Reset type: XRSn

15-2RESERVEDR-00hReserved
1XRSnR-0/W1S0hWriting a 1 to this field generates a XRSn like reset.
Writing a 0 has no effect.
Note: Writing to this pin will pull the XRSn pin low for 512 INTOSC1 clock cycles.

Reset type: XRSn

0CPU1RSnR-0/W1S0hWriting a 1 to this field generates a reset to to CPU1.
Writing a 0 has no effect.

Reset type: XRSn

3.16.4.25 LPMCR Register (Offset = 76h) [Reset = 000000FCh]

LPMCR is shown in Figure 3-82 and described in Table 3-86.

Return to the Summary Table.

LPM Control Register

Figure 3-82 LPMCR Register
3130292827262524
RESERVEDRESERVED
R/W1S-0hR-0-0h
2322212019181716
RESERVEDRESERVED
R-0-0hR/W-0h
15141312111098
WDINTERESERVED
R/W-0hR-0-0h
76543210
QUALSTDBYLPM
R/W-3FhR/W-0h
Table 3-86 LPMCR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W1S0hReserved
30-18RESERVEDR-00hReserved
17-16RESERVEDR/W0hReserved
15WDINTER/W0hWhen this bit is set to 1, it enables the watchdog interrupt signal to wake the device from STANDBY mode.

Note:
[1] To use this signal, the user must also enable the WDINTn signal using the WDENINT bit in the SCSR register. This signal will not wake the device from HALT mode because the clock to watchdog module is turned off

Reset type: SYSRSn

14-8RESERVEDR-00hReserved
7-2QUALSTDBYR/W3FhSelect number of OSCCLK clock cycles to qualify the selected inputs when waking the from STANDBY mode:

000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper wake up.

Reset type: SYSRSn

1-0LPMR/W0hThese bits set the low power mode for the device. Takes effect when CPU executes the IDLE instruction (when IDLE instruction is out of EXE Phase of the Pipeline)

00: IDLE Mode
01: STANDBY Mode
1x: HALT Mode

Reset type: SYSRSn

3.16.4.26 GPIOLPMSEL0 Register (Offset = 78h) [Reset = 00000000h]

GPIOLPMSEL0 is shown in Figure 3-83 and described in Table 3-87.

Return to the Summary Table.

GPIO LPM Wakeup select registers

Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the selected pin.

Figure 3-83 GPIOLPMSEL0 Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-87 GPIOLPMSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

30GPIO30R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

29GPIO29R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

28GPIO28R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

27GPIO27R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

26GPIO26R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

25GPIO25R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

24GPIO24R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

23GPIO23R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

22GPIO22R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

21GPIO21R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

20GPIO20R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

19GPIO19R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

18GPIO18R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

17GPIO17R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

16GPIO16R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

15GPIO15R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

14GPIO14R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

13GPIO13R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

12GPIO12R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

11GPIO11R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

10GPIO10R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

9GPIO9R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

8GPIO8R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

7GPIO7R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

6GPIO6R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

5GPIO5R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

4GPIO4R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

3GPIO3R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

2GPIO2R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

1GPIO1R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

0GPIO0R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

3.16.4.27 GPIOLPMSEL1 Register (Offset = 7Ah) [Reset = 00000000h]

GPIOLPMSEL1 is shown in Figure 3-84 and described in Table 3-88.

Return to the Summary Table.

GPIO LPM Wakeup select registers

Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the selected pin.

Figure 3-84 GPIOLPMSEL1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDGPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39RESERVEDGPIO37RESERVEDGPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-88 GPIOLPMSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28GPIO60R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

27GPIO59R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

26GPIO58R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

25GPIO57R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

24GPIO56R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

23GPIO55R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

22GPIO54R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

21GPIO53R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

20GPIO52R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

19GPIO51R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

18GPIO50R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

17GPIO49R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

16GPIO48R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

15GPIO47R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

14GPIO46R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

13GPIO45R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

12GPIO44R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

11GPIO43R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

10GPIO42R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

9GPIO41R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

8GPIO40R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

7GPIO39R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO37R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

4RESERVEDR/W0hReserved
3GPIO35R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

2GPIO34R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

1GPIO33R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

0GPIO32R/W0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit

Reset type: SYSRSn

3.16.4.28 TMR2CLKCTL Register (Offset = 7Ch) [Reset = 00000000h]

TMR2CLKCTL is shown in Figure 3-85 and described in Table 3-89.

Return to the Summary Table.

Timer2 Clock Measurement functionality control register
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.

Figure 3-85 TMR2CLKCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDTMR2CLKPRESCALETMR2CLKSRCSEL
R-0-0hR/W-0hR/W-0h
Table 3-89 TMR2CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5-3TMR2CLKPRESCALER/W0hCPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale value for the selected clock source for CPU Timer 2:
000: /1 (default on reset)
001: /2,
010: /4
011: /8
100: /16
101: spare (defaults to /16)
110: spare (defaults to /16)
111: spare (defaults to /16)

Note:
[1] The CPU Timer2s Clock sync logic detects an input clock edge when configured for any clock source other than SYSCLK and generates an appropriate clock pulse to the CPU timer2. If SYSCLK is approximately the same or less then the input clock source, then the user would need to configure the pre-scale value such that SYSCLK is at least twice as fast as the pre-scaled value.

Reset type: SYSRSn

2-0TMR2CLKSRCSELR/W0hCPU Timer 2 Clock Source Select Bit: This bit selects the source for CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
Other values = reserved

Reset type: SYSRSn

3.16.4.29 RESCCLR Register (Offset = 7Eh) [Reset = 00000000h]

RESCCLR is shown in Figure 3-86 and described in Table 3-90.

Return to the Summary Table.

Reset Cause Clear Register

Figure 3-86 RESCCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDSIMRESET_XRSnSIMRESET_CPU1RSnRESERVEDSCCRESETn
R-0-0hW1C-0hW1C-0hR-0-0hW1S-0h
76543210
RESERVEDRESERVEDHWBISTnRESERVEDNMIWDRSnWDRSnXRSnPOR
R-0-0hW1S-0hW1S-0hR-0-0hW1S-0hW1S-0hW1S-0hW1S-0h
Table 3-90 RESCCLR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11SIMRESET_XRSnW1C0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

10SIMRESET_CPU1RSnW1C0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

9RESERVEDR-00hReserved
8SCCRESETnW1S0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

7RESERVEDR-00hReserved
6RESERVEDW1S0hReserved
5HWBISTnW1S0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

4RESERVEDR-00hReserved
3NMIWDRSnW1S0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

2WDRSnW1S0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

1XRSnW1S0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

0PORW1S0hClear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.

Reset type: SYSRSn

3.16.4.30 RESC Register (Offset = 80h) [Reset = X0000003h]

RESC is shown in Figure 3-87 and described in Table 3-91.

Return to the Summary Table.

Reset Cause register

Figure 3-87 RESC Register
3130292827262524
DCONXRSn_pin_statusRESERVED
R-0hR-XR-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDSIMRESET_XRSnSIMRESET_CPU1RSnRESERVEDSCCRESETn
R-0-0hR-0hR-0hR-0-0hR-0h
76543210
RESERVEDRESERVEDHWBISTnRESERVEDNMIWDRSnWDRSnXRSnPOR
R-0-0hR-0hR-0hR-0-0hR-0hR-0hR-1hR-1h
Table 3-91 RESC Register Field Descriptions
BitFieldTypeResetDescription
31DCONR0hReading this bit provides the status of debugger connection to the C28x CPU.
0 : Debugger is not connected to the C28x CPU
1 : Debugger is connected to the C28x CPU

Notes:
[1] This bit is connected to the DCON o/p signal of the C28x CPU

Reset type: N/A

30XRSn_pin_statusRXReading this bit provides the current status of the XRSn pin. Reset value is reflective of the pin status.

Reset type: N/A

29-16RESERVEDR-00hReserved
15-12RESERVEDR-00hReserved
11SIMRESET_XRSnR0hIf this bit is set, indicates that the device was reset by SIMRESET_XRSn

Reset type: PORESETn

10SIMRESET_CPU1RSnR0hIf this bit is set, indicates that the device was reset by SIMRESET_CPU1RSn

Reset type: PORESETn

9RESERVEDR-00hReserved
8SCCRESETnR0hIf this bit is set, indicates that the device was reset by SCCRESETn (fired by DCSM).

Reset type: PORESETn

7RESERVEDR-00hReserved
6RESERVEDR0hReserved
5HWBISTnR0hIf this bit is set, indicates that the device was reset by HWBIST.

Reset type: PORESETn

4RESERVEDR-00hReserved
3NMIWDRSnR0hIf this bit is set, indicates that the device was reset by NMIWDRSn.
Note: To know the exact cause of NMI after the reset, software needs to read NMISHDFLG registers

Reset type: PORESETn

2WDRSnR0hIf this bit is set, indicates that the device was reset by WDRSn.
Note:
[1] A bit inside WD module also provides the same information. This bit is present to keep things consistent. This register is a one-stop shop for the software to know the reset cause for the C28x core.

Reset type: PORESETn

1XRSnR1hIf this bit is set, indicates that the device was reset by XRSn.

Reset type: PORESETn

0PORR1hIf this bit is set, indicates that the device was reset by PORn/BORn.

Reset type: PORESETn

3.16.4.31 MCANWAKESTATUS Register (Offset = 98h) [Reset = 00000000h]

MCANWAKESTATUS is shown in Figure 3-88 and described in Table 3-92.

Return to the Summary Table.

MCAN Wake Status Register

Figure 3-88 MCANWAKESTATUS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKE
R-0hR-0h
Table 3-92 MCANWAKESTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0WAKER0h0 : wakeup event has not occured.
1 : wakeup event has occured.

Reset type: SYSRSn

3.16.4.32 MCANWAKESTATUSCLR Register (Offset = 9Ah) [Reset = 00000000h]

MCANWAKESTATUSCLR is shown in Figure 3-89 and described in Table 3-93.

Return to the Summary Table.

MCAN Wake Status Clear Register

Figure 3-89 MCANWAKESTATUSCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKE
R-0hR-0/W1S-0h
Table 3-93 MCANWAKESTATUSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0WAKER-0/W1S0h0 : No effect.
1 : Clears WAKE bit of MCANWAKESTATUS register

Reset type: SYSRSn

3.16.4.33 CLKSTOPREQ Register (Offset = 9Ch) [Reset = 00000000h]

CLKSTOPREQ is shown in Figure 3-90 and described in Table 3-94.

Return to the Summary Table.

Peripheral Clock Stop Request Register
Note: This register exists only on CPU1

Figure 3-90 CLKSTOPREQ Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVEDRESERVEDMCAN_A
R-0-0hR-0-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR-0-0hR/W-0hR-0-0hR/W-0h
Table 3-94 CLKSTOPREQ Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hWrite to any of the bits in this register will succeed only if a value of 0x5634 is written to the KEY field.

Reset type: SYSRSn

15-12RESERVEDR-00hReserved
11-9RESERVEDR-00hReserved
8MCAN_AR/W0hMCAN_A Clock Stop Request Bit
0: If clock to MCAN_A is turned off, it will be turned on, else no effect.
1: Clock stop request toMCAN_A
Note: Once set, this bit is cleared when clock to MCAN_A is turned on as a result of a wakeup event in hardware

Reset type: SYSRSn

7-6RESERVEDR-00hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR-00hReserved
2RESERVEDR/W0hReserved
1RESERVEDR-00hReserved
0RESERVEDR/W0hReserved

3.16.4.34 CLKSTOPACK Register (Offset = 9Eh) [Reset = 00000000h]

CLKSTOPACK is shown in Figure 3-91 and described in Table 3-95.

Return to the Summary Table.

Peripheral Clock Stop Ackonwledge Register
Note: This register exists only on CPU1

Figure 3-91 CLKSTOPACK Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDMCAN_A
R-0-0hR-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR-0hR-0hR-0-0hR-0hR-0-0hR-0h
Table 3-95 CLKSTOPACK Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR-00hReserved
8MCAN_AR0hMCAN_A Clock Stop Acknowledge Bit
0: Clock stop request not acknowledged
1: Clock stop acknowledged

Reset type: SYSRSn

7-6RESERVEDR-00hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3RESERVEDR-00hReserved
2RESERVEDR0hReserved
1RESERVEDR-00hReserved
0RESERVEDR0hReserved