SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
In addition to the pipeline there are a few other behaviors of the DMA that affect the total throughput:
For example, to transfer 128 16-bit words from GS0 RAM to GS3 RAM, a channel can be configured to transfer 8 bursts of 16 words/burst. This gives:
8 bursts * [(3 cycles/word * 16 words/burst) + 1] = 392 cycles |
If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size is configured to 32 bits), the transfer can take:
8 bursts * [(3 cycles/word * 8 words/burst) + 1] = 200 cycles |
The DMA module consists of a 3-stage pipeline as shown in Figure 12-5 and Figure 12-6.