SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
32-Bit Floating-Point Subtraction with Parallel Move
MRd | CLA floating-point destination register (MR0 to MR3) for the MSUBF32
operation MRd cannot be the same register as MRa |
MRe | CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation |
MRf | CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation |
MRa | CLA floating-point destination register (MR0 to MR3) for the MMOV32 operation MRa cannot be the same register as MRd |
mem32 | 32-bit memory location accessed using one of the available addressing modes. Source for the MMOV32 operation. |
LSW: mmmm mmmm mmmm mmmm
MSW: 0010 ffee ddaa addr
Subtract the contents of two floating-point registers and move from memory to a floating-point register.
MRd = MRe - MRf;
MRa = [mem32];
The destination register for the MSUBF32 and the MMOV32 must be unique. That is, MRa cannot be the same register as MRd.
This instruction modifies the following flags in the MSTF register:
Flag | TF | ZF | NF | LUF | LVF |
---|---|---|---|---|---|
Modified | No | Yes | Yes | Yes | Yes |
The MSTF register flags are modified as follows:
The MMOV32 instruction sets the NF and ZF flags.
Both MSUBF32 and MMOV32 complete in a single cycle.
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }