SPRUIW9 User guide

SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

1
Read This First
1. About This Manual
2. Notational Conventions
3. Glossary
4. Related Documentation From Texas Instruments
5. Support Resources
6. Trademarks
1 C2000™ Microcontrollers Software Support
1. 1.1 Introduction
2. 1.2 C2000Ware Structure
3. 1.3 Documentation
4. 1.4 Devices
5. 1.5 Libraries
6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
7. 1.7 SysConfig and PinMUX Tool
2 C28x Processor
1. 2.1 Introduction
2. 2.2 C28X Related Collateral
3. 2.3 Features
4. 2.4 Floating-Point Unit
5. 2.5 Trigonometric Math Unit (TMU)
6. 2.6 VCRC Unit
3 System Control and Interrupts
1. 3.1 Introduction
2. 3.2 Power Management
3. 3.3 Device Identification and Configuration Registers
4. 3.4 Resets
5. 3.5 Peripheral Interrupts
6. 3.6 Exceptions and Non-Maskable Interrupts
7. 3.7 Clocking
8. 3.8 32-Bit CPU Timers 0/1/2
9. 3.9 Watchdog Timer
10. 3.10 Low-Power Modes
11. 3.11 Memory Controller Module
12. 3.12 JTAG
  1. 3.12.1 JTAG Noise and TAP_STATUS
13. 3.13 Live Firmware Update
14. 3.14 System Control Register Configuration Restrictions
15. 3.15 Software
16. 3.16 System Control Registers
4 ROM Code and Peripheral Booting
1. 4.1 Introduction
2. 4.2 ROM Related Collateral
3. 4.3 Device Boot Sequence
4. 4.4 Device Boot Modes
  1. 4.4.1 Default Boot Modes
  2. 4.4.2 Custom Boot Modes
5. 4.5 Device Boot Configurations
6. 4.6 Device Boot Flow Diagrams
7. 4.7 Device Reset and Exception Handling
  1. 4.7.1 Reset Causes and Handling
  2. 4.7.2 Exceptions and Interrupts Handling
8. 4.8 Boot ROM Description
9. 4.9 Application Notes for Using the Bootloaders
  1. 4.9.1 Bootloader Data Stream Structure
    1. 4.9.1.1 Data Stream Structure 8-bit
  2. 4.9.2 The C2000 Hex Utility
    1. 4.9.2.1 HEX2000.exe Command Syntax
10. 4.10 Software
  1. 4.10.1 BOOT Examples
5 Dual Code Security Module (DCSM)
1. 5.1 Introduction
  1. 5.1.1 DCSM Related Collateral
2. 5.2 Functional Description
3. 5.3 Flash and OTP Erase/Program
4. 5.4 Secure Copy Code
5. 5.5 SecureCRC
6. 5.6 CSM Impact on Other On-Chip Resources
7. 5.7 Incorporating Code Security in User Applications
8. 5.8 Software
  1. 5.8.1 DCSM Examples
    1. 5.8.1.1 Empty DCSM Tool Example
9. 5.9 DCSM Registers
6 Flash Module
1. 6.1 Introduction to Flash and OTP Memory
2. 6.2 Flash Bank, OTP, and Pump
3. 6.3 Flash Module Controller (FMC)
4. 6.4 Flash and OTP Memory Power-Down Modes and Wakeup
5. 6.5 Active Grace Period
6. 6.6 Flash and OTP Memory Performance
7. 6.7 Flash Read Interface
  1. 6.7.1 C28x-FMC Flash Read Interface
    1. 6.7.1.1 Standard Read Mode
    2. 6.7.1.2 Prefetch Mode
      1. 6.7.1.2.1 Data Cache
8. 6.8 Flash Erase and Program
9. 6.9 Error Correction Code (ECC) Protection
10. 6.10 Reserved Locations Within Flash and OTP Memory
11. 6.11 Migrating an Application from RAM to Flash
12. 6.12 Procedure to Change the Flash Control Registers
13. 6.13 Software
  1. 6.13.1 FLASH Examples
14. 6.14 Flash Registers
7 Control Law Accelerator (CLA)
1. 7.1 Introduction
2. 7.2 CLA Interface
3. 7.3 CLA and CPU Arbitration
  1. 7.3.1 CLA Message RAM
  2. 7.3.2 Peripheral Registers (ePWM, HRPWM, Comparator)
4. 7.4 CLA Configuration and Debug
5. 7.5 Pipeline
6. 7.6 Software
  1. 7.6.1 CLA Examples
7. 7.7 Instruction Set
  1. 7.7.1 Instruction Descriptions
  2. 7.7.2 Addressing Modes and Encoding
  3. 7.7.3 Instructions
    1. MABSF32 MRa, MRb
    2. MADD32 MRa, MRb, MRc
    3. MADDF32 MRa, #16FHi, MRb
    4. MADDF32 MRa, MRb, #16FHi
    5. MADDF32 MRa, MRb, MRc
    6. MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
    7. MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    8. MAND32 MRa, MRb, MRc
    9. MASR32 MRa, #SHIFT
    10. MBCNDD 16BitDest [, CNDF]
    11. MCCNDD 16BitDest [, CNDF]
    12. MCMP32 MRa, MRb
    13. MCMPF32 MRa, MRb
    14. MCMPF32 MRa, #16FHi
    15. MDEBUGSTOP
    16. MEALLOW
    17. MEDIS
    18. MEINVF32 MRa, MRb
    19. MEISQRTF32 MRa, MRb
    20. MF32TOI16 MRa, MRb
    21. MF32TOI16R MRa, MRb
    22. MF32TOI32 MRa, MRb
    23. MF32TOUI16 MRa, MRb
    24. MF32TOUI16R MRa, MRb
    25. MF32TOUI32 MRa, MRb
    26. MFRACF32 MRa, MRb
    27. MI16TOF32 MRa, MRb
    28. MI16TOF32 MRa, mem16
    29. MI32TOF32 MRa, mem32
    30. MI32TOF32 MRa, MRb
    31. MLSL32 MRa, #SHIFT
    32. MLSR32 MRa, #SHIFT
    33. MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
    34. MMAXF32 MRa, MRb
    35. MMAXF32 MRa, #16FHi
    36. MMINF32 MRa, MRb
    37. MMINF32 MRa, #16FHi
    38. MMOV16 MARx, MRa, #16I
    39. MMOV16 MARx, mem16
    40. MMOV16 mem16, MARx
    41. MMOV16 mem16, MRa
    42. MMOV32 mem32, MRa
    43. MMOV32 mem32, MSTF
    44. MMOV32 MRa, mem32 [, CNDF]
    45. MMOV32 MRa, MRb [, CNDF]
    46. MMOV32 MSTF, mem32
    47. MMOVD32 MRa, mem32
    48. MMOVF32 MRa, #32F
    49. MMOVI16 MARx, #16I
    50. MMOVI32 MRa, #32FHex
    51. MMOVIZ MRa, #16FHi
    52. MMOVZ16 MRa, mem16
    53. MMOVXI MRa, #16FLoHex
    54. MMPYF32 MRa, MRb, MRc
    55. MMPYF32 MRa, #16FHi, MRb
    56. MMPYF32 MRa, MRb, #16FHi
    57. MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
    58. MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    59. MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    60. MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
    61. MNEGF32 MRa, MRb[, CNDF]
    62. MNOP
    63. MOR32 MRa, MRb, MRc
    64. MRCNDD [CNDF]
    65. MSETFLG FLAG, VALUE
    66. MSTOP
    67. MSUB32 MRa, MRb, MRc
    68. MSUBF32 MRa, MRb, MRc
    69. MSUBF32 MRa, #16FHi, MRb
    70. MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    71. MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    72. MSWAPF MRa, MRb [, CNDF]
    73. MTESTTF CNDF
    74. MUI16TOF32 MRa, mem16
    75. MUI16TOF32 MRa, MRb
    76. MUI32TOF32 MRa, mem32
    77. MUI32TOF32 MRa, MRb
    78. MXOR32 MRa, MRb, MRc
8. 7.8 CLA Registers
8 Dual-Clock Comparator (DCC)
1. 8.1 Introduction
  1. 8.1.1 Features
  2. 8.1.2 Block Diagram
2. 8.2 Module Operation
3. 8.3 Interrupts
4. 8.4 Software
  1. 8.4.1 DCC Examples
5. 8.5 DCC Registers
9 Background CRC-32 (BGCRC)
1. 9.1 Introduction
2. 9.2 Functional Description
3. 9.3 Application of the BGCRC
4. 9.4 Software
  1. 9.4.1 BGCRC Examples
5. 9.5 BGCRC Registers
10General-Purpose Input/Output (GPIO)
1. 10.1 Introduction
  1. 10.1.1 GPIO Related Collateral
2. 10.2 Configuration Overview
3. 10.3 Digital Inputs on ADC Pins (AIOs)
4. 10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
5. 10.5 Digital General-Purpose I/O Control
6. 10.6 Input Qualification
7. 10.7 GPIO and Peripheral Muxing
  1. 10.7.1 GPIO Muxing
  2. 10.7.2 Peripheral Muxing
8. 10.8 Internal Pullup Configuration Requirements
9. 10.9 Software
  1. 10.9.1 GPIO Examples
  2. 10.9.2 LED Examples
10. 10.10 GPIO Registers
11Crossbar (X-BAR)
1. 11.1 Input X-BAR and CLB Input X-BAR
  1. 11.1.1 CLB Input X-BAR
2. 11.2 ePWM, CLB, and GPIO Output X-BAR
3. 11.3 XBAR Registers
12Direct Memory Access (DMA)
1. 12.1 Introduction
  1. 12.1.1 Features
  2. 12.1.2 Block Diagram
2. 12.2 Architecture
  1. 12.2.1 Peripheral Interrupt Event Trigger Sources
  2. 12.2.2 DMA Bus
3. 12.3 Address Pointer and Transfer Control
4. 12.4 Pipeline Timing and Throughput
5. 12.5 CPU and CLA Arbitration
6. 12.6 Channel Priority
  1. 12.6.1 Round-Robin Mode
  2. 12.6.2 Channel 1 High-Priority Mode
7. 12.7 Overrun Detection Feature
8. 12.8 Software
  1. 12.8.1 DMA Examples
    1. 12.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
    2. 12.8.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
9. 12.9 DMA Registers
13Embedded Real-time Analysis and Diagnostic (ERAD)
1. 13.1 Introduction
  1. 13.1.1 ERAD Related Collateral
2. 13.2 Enhanced Bus Comparator Unit
  1. 13.2.1 Enhanced Bus Comparator Unit Operations
  2. 13.2.2 Event Masking and Exporting
3. 13.3 System Event Counter Unit
4. 13.4 ERAD Ownership, Initialization and Reset
5. 13.5 ERAD Programming Sequence
  1. 13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
  2. 13.5.2 Timer and Counter Programming Sequence
6. 13.6 Cyclic Redundancy Check Unit
  1. 13.6.1 CRC Unit Qualifier
  2. 13.6.2 CRC Unit Programming Sequence
7. 13.7 Program Counter Trace
8. 13.8 Software
  1. 13.8.1 ERAD Examples
9. 13.9 ERAD Registers
14Host Interface Controller (HIC)
1. 14.1 Introduction
2. 14.2 Functional Description
3. 14.3 Operation
4. 14.4 Usage Scenarious for Reduced Number of Pins
5. 14.5 Software
  1. 14.5.1 HIC Examples
6. 14.6 HIC Registers
15Analog Subsystem
1. 15.1 Introduction
  1. 15.1.1 Features
  2. 15.1.2 Block Diagram
2. 15.2 Optimizing Power-Up Time
3. 15.3 Digital Inputs on ADC Pins (AIOs)
4. 15.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
5. 15.5 Analog Pins and Internal Connections
6. 15.6 Analog Subsystem Registers
16Analog-to-Digital Converter (ADC)
1. 16.1 Introduction
2. 16.2 ADC Configurability
3. 16.3 SOC Principle of Operation
4. 16.4 SOC Configuration Examples
5. 16.5 ADC Conversion Priority
6. 16.6 Burst Mode
  1. 16.6.1 Burst Mode Example
  2. 16.6.2 Burst Mode Priority Example
7. 16.7 EOC and Interrupt Operation
8. 16.8 Post-Processing Blocks
9. 16.9 Opens/Shorts Detection Circuit (OSDETECT)
10. 16.10 Power-Up Sequence
11. 16.11 ADC Calibration
  1. 16.11.1 ADC Zero Offset Calibration
12. 16.12 ADC Timings
  1. 16.12.1 ADC Timing Diagrams
13. 16.13 Additional Information
14. 16.14 Software
  1. 16.14.1 ADC Examples
15. 16.15 ADC Registers
17Buffered Digital-to-Analog Converter (DAC)
1. 17.1 Introduction
2. 17.2 Using the DAC
3. 17.3 Lock Registers
4. 17.4 Software
  1. 17.4.1 DAC Examples
5. 17.5 DAC Registers
18Comparator Subsystem (CMPSS)
1. 18.1 Introduction
2. 18.2 Comparator
3. 18.3 Reference DAC
4. 18.4 Ramp Generator
5. 18.5 Digital Filter
  1. 18.5.1 Filter Initialization Sequence
6. 18.6 Using the CMPSS
7. 18.7 Software
  1. 18.7.1 CMPSS Examples
    1. 18.7.1.1 CMPSS Asynchronous Trip
    2. 18.7.1.2 CMPSS Digital Filter Configuration
8. 18.8 CMPSS Registers
19Sigma Delta Filter Module (SDFM)
1. 19.1 Introduction
2. 19.2 Configuring Device Pins
3. 19.3 Input Qualification
4. 19.4 Input Control Unit
5. 19.5 SDFM Clock Control
6. 19.6 Sinc Filter
  1. 19.6.1 Data Rate and Latency of the Sinc Filter
7. 19.7 Data (Primary) Filter Unit
8. 19.8 Comparator (Secondary) Filter Unit
9. 19.9 Theoretical SDFM Filter Output
10. 19.10 Interrupt Unit
  1. 19.10.1 SDFM (SDyERR) Interrupt Sources
  2. 19.10.2 Data Ready (DRINT) Interrupt Sources
11. 19.11 Software
  1. 19.11.1 SDFM Examples
12. 19.12 SDFM Registers
20Enhanced Pulse Width Modulator (ePWM)
1. 20.1 Introduction
  1. 20.1.1 EPWM Related Collateral
  2. 20.1.2 Submodule Overview
2. 20.2 Configuring Device Pins
3. 20.3 ePWM Modules Overview
4. 20.4 Time-Base (TB) Submodule
5. 20.5 Counter-Compare (CC) Submodule
6. 20.6 Action-Qualifier (AQ) Submodule
7. 20.7 Dead-Band Generator (DB) Submodule
8. 20.8 PWM Chopper (PC) Submodule
9. 20.9 Trip-Zone (TZ) Submodule
10. 20.10 Event-Trigger (ET) Submodule
  1. 20.10.1 Operational Overview of the ePWM Event-Trigger Submodule
11. 20.11 Digital Compare (DC) Submodule
12. 20.12 ePWM Crossbar (X-BAR)
13. 20.13 Applications to Power Topologies
14. 20.14 Register Lock Protection
15. 20.15 High-Resolution Pulse Width Modulator (HRPWM)
  1. 20.15.1 Operational Description of HRPWM
  2. 20.15.2 SFO Library Software - SFO_TI_Build_V8.lib
    1. 20.15.2.1 Scale Factor Optimizer Function - int SFO()
    2. 20.15.2.2 Software Usage
      1. 20.15.2.2.1 A Sample of How to Add "Include" Files
      2. 963
      3. 20.15.2.2.2 Declaring an Element
      4. 965
      5. 20.15.2.2.3 Initializing With a Scale Factor Value
      6. 967
      7. 20.15.2.2.4 SFO Function Calls
16. 20.16 Software
  1. 20.16.1 EPWM Examples
  2. 20.16.2 HRPWM Examples
17. 20.17 ePWM Registers
21Enhanced Capture (eCAP)
1. 21.1 Introduction
  1. 21.1.1 Features
  2. 21.1.2 ECAP Related Collateral
2. 21.2 Description
3. 21.3 Configuring Device Pins for the eCAP
4. 21.4 Capture and APWM Operating Mode
5. 21.5 Capture Mode Description
6. 21.6 Application of the eCAP Module
7. 21.7 Application of the APWM Mode
  1. 21.7.1 Example 1 - Simple PWM Generation (Independent Channels)
8. 21.8 Software
  1. 21.8.1 ECAP Examples
9. 21.9 eCAP Registers
22High Resolution Capture (HRCAP)
1. 22.1 Introduction
2. 22.2 Operational Details
3. 22.3 Known Exceptions
4. 22.4 Software
  1. 22.4.1 HRCAP Examples
    1. 22.4.1.1 HRCAP Capture and Calibration Example
5. 22.5 HRCAP Registers
23Enhanced Quadrature Encoder Pulse (eQEP)
1. 23.1 Introduction
  1. 23.1.1 EQEP Related Collateral
2. 23.2 Configuring Device Pins
3. 23.3 Description
4. 23.4 Quadrature Decoder Unit (QDU)
5. 23.5 Position Counter and Control Unit (PCCU)
6. 23.6 eQEP Edge Capture Unit
7. 23.7 eQEP Watchdog
8. 23.8 eQEP Unit Timer Base
9. 23.9 QMA Module
  1. 23.9.1 Modes of Operation
    1. 23.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
    2. 23.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
  2. 23.9.2 Interrupt and Error Generation
10. 23.10 eQEP Interrupt Structure
11. 23.11 Software
  1. 23.11.1 EQEP Examples
12. 23.12 eQEP Registers
24Serial Peripheral Interface (SPI)
1. 24.1 Introduction
2. 24.2 System-Level Integration
3. 24.3 SPI Operation
4. 24.4 Programming Procedure
5. 24.5 Software
  1. 24.5.1 SPI Examples
6. 24.6 SPI Registers
25Serial Communications Interface (SCI)
1. 25.1 Introduction
2. 25.2 Architecture
3. 25.3 SCI Module Signal Summary
4. 25.4 Configuring Device Pins
5. 25.5 Multiprocessor and Asynchronous Communication Modes
6. 25.6 SCI Programmable Data Format
7. 25.7 SCI Multiprocessor Communication
8. 25.8 Idle-Line Multiprocessor Mode
9. 25.9 Address-Bit Multiprocessor Mode
  1. 25.9.1 Sending an Address
10. 25.10 SCI Communication Format
  1. 25.10.1 Receiver Signals in Communication Modes
  2. 25.10.2 Transmitter Signals in Communication Modes
11. 25.11 SCI Port Interrupts
  1. 25.11.1 Break Detect
12. 25.12 SCI Baud Rate Calculations
13. 25.13 SCI Enhanced Features
14. 25.14 Software
  1. 25.14.1 SCI Examples
15. 25.15 SCI Registers
26Inter-Integrated Circuit Module (I2C)
1. 26.1 Introduction
2. 26.2 Configuring Device Pins
3. 26.3 I2C Module Operational Details
4. 26.4 Interrupt Requests Generated by the I2C Module
  1. 26.4.1 Basic I2C Interrupt Requests
  2. 26.4.2 I2C FIFO Interrupts
5. 26.5 Resetting or Disabling the I2C Module
6. 26.6 Software
  1. 26.6.1 I2C Examples
7. 26.7 I2C Registers
27Power Management Bus Module (PMBus)
1. 27.1 Introduction
2. 27.2 Configuring Device Pins
3. 27.3 Slave Mode Operation
  1. 27.3.1 Configuration
  2. 27.3.2 Message Handling
4. 27.4 Master Mode Operation
  1. 27.4.1 Configuration
  2. 27.4.2 Message Handling
5. 27.5 PMBus Registers
28Controller Area Network (CAN)
1. 28.1 Introduction
2. 28.2 Functional Description
  1. 28.2.1 Configuring Device Pins
  2. 28.2.2 Address/Data Bus Bridge
3. 28.3 Operating Modes
4. 28.4 Multiple Clock Source
5. 28.5 Interrupt Functionality
6. 28.6 DMA Functionality
7. 28.7 Parity Check Mechanism
  1. 28.7.1 Behavior on Parity Error
8. 28.8 Debug Mode
9. 28.9 Module Initialization
10. 28.10 Configuration of Message Objects
11. 28.11 Message Handling
12. 28.12 CAN Bit Timing
  1. 28.12.1 Bit Time and Bit Rate
  2. 28.12.2 Configuration of the CAN Bit Timing
13. 28.13 Message Interface Register Sets
  1. 28.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
  2. 28.13.2 Message Interface Register Set 3 (IF3)
14. 28.14 Message RAM
15. 28.15 Software
  1. 28.15.1 CAN Examples
16. 28.16 CAN Registers
29Modular Controller Area Network (MCAN)
1. 29.1 MCAN Introduction
  1. 29.1.1 MCAN Related Collateral
  2. 29.1.2 MCAN Features
2. 29.2 MCAN Environment
3. 29.3 CAN Network Basics
4. 29.4 MCAN Integration
5. 29.5 MCAN Functional Description
6. 29.6 Software
  1. 29.6.1 MCAN Examples
7. 29.7 MCAN Registers
30Local Interconnect Network (LIN)
1. 30.1 Introduction
2. 30.2 Serial Communications Interface Module
3. 30.3 Local Interconnect Network Module
4. 30.4 Low-Power Mode
5. 30.5 Emulation Mode
6. 30.6 Software
  1. 30.6.1 LIN Examples
7. 30.7 SCI/LIN Registers
31Fast Serial Interface (FSI)
1. 31.1 Introduction
  1. 31.1.1 FSI Related Collateral
  2. 31.1.2 FSI Features
2. 31.2 System-level Integration
3. 31.3 FSI Functional Description
4. 31.4 FSI Programing Guide
5. 31.5 Software
  1. 31.5.1 FSI Examples
6. 31.6 FSI Registers
32Configurable Logic Block (CLB)
1. 32.1 Introduction
  1. 32.1.1 CLB Related Collateral
2. 32.2 Description
  1. 32.2.1 CLB Clock
3. 32.3 CLB Input/Output Connection
4. 32.4 CLB Tile
5. 32.5 CPU Interface
  1. 32.5.1 Register Description
  2. 32.5.2 Non-Memory Mapped Registers
6. 32.6 DMA Access
7. 32.7 CLB Data Export Through SPI RX Buffer
8. 32.8 Software
  1. 32.8.1 CLB Examples
9. 32.9 CLB Registers
33Advanced Encryption Standard (AES) Accelerator
1. 33.1 Introduction
  1. 33.1.1 AES Block Diagram
  2. 33.1.2 AES Algorithm
2. 33.2 AES Operating Modes
3. 33.3 Extended and Combined Modes of Operations
4. 33.4 AES Module Programming Guide
  1. 33.4.1 AES Low-Level Programming Models
5. 33.5 Software
  1. 33.5.1 AES Examples
6. 33.6 AES Registers
34Embedded Pattern Generator (EPG)
1. 34.1 Introduction
2. 34.2 Clock Generator Modules
  1. 34.2.1 DCLK (50% duty cycle clock)
  2. 34.2.2 Clock Stop
3. 34.3 Signal Generator Module
4. 34.4 EPG Peripheral Signal Mux Selection
5. 34.5 EPG Example Use Cases
6. 34.6 EPG Interrupt
7. 34.7 Software
  1. 34.7.1 EPG Examples
8. 34.8 EPG Registers
35Revision History

7.8.4 CLA_REGS Registers

Table 7-35 lists the memory-mapped registers for the CLA_REGS registers. All register offset addresses not listed in Table 7-35 should be considered as reserved locations and the register contents should not be modified.

Table 7-35 CLA_REGS Registers

Offset	Acronym	Register Name	Write Protection	Section
0h	MVECT1	Task Interrupt Vector	EALLOW	Go
1h	MVECT2	Task Interrupt Vector	EALLOW	Go
2h	MVECT3	Task Interrupt Vector	EALLOW	Go
3h	MVECT4	Task Interrupt Vector	EALLOW	Go
4h	MVECT5	Task Interrupt Vector	EALLOW	Go
5h	MVECT6	Task Interrupt Vector	EALLOW	Go
6h	MVECT7	Task Interrupt Vector	EALLOW	Go
7h	MVECT8	Task Interrupt Vector	EALLOW	Go
10h	MCTL	Control Register	EALLOW	Go
1Bh	_MVECTBGRNDACTIVE	Active register for MVECTBGRND.	EALLOW	Go
1Ch	SOFTINTEN	CLA Software Interrupt Enable Register		Go
1Dh	_MSTSBGRND	Status register for the back ground task.	EALLOW	Go
1Eh	_MCTLBGRND	Control register for the back ground task.	EALLOW	Go
1Fh	_MVECTBGRND	Vector for the back ground task.	EALLOW	Go
20h	MIFR	Interrupt Flag Register	EALLOW	Go
21h	MIOVF	Interrupt Overflow Flag Register	EALLOW	Go
22h	MIFRC	Interrupt Force Register	EALLOW	Go
23h	MICLR	Interrupt Flag Clear Register	EALLOW	Go
24h	MICLROVF	Interrupt Overflow Flag Clear Register	EALLOW	Go
25h	MIER	Interrupt Enable Register	EALLOW	Go
26h	MIRUN	Interrupt Run Status Register	EALLOW	Go
28h	_MPC	CLA Program Counter		Go
2Ah	_MAR0	CLA Auxiliary Register 0		Go
2Bh	_MAR1	CLA Auxiliary Register 1		Go
2Eh	_MSTF	CLA Floating-Point Status Register		Go
30h	_MR0	CLA Floating-Point Result Register 0		Go
34h	_MR1	CLA Floating-Point Result Register 1		Go
38h	_MR2	CLA Floating-Point Result Register 2		Go
3Ch	_MR3	CLA Floating-Point Result Register 3		Go
42h	_MPSACTL	CLA PSA Control Register	EALLOW	Go
44h	_MPSA1	CLA PSA1 Register	EALLOW	Go
46h	_MPSA2	CLA PSA2 Register	EALLOW	Go

Complex bit access types are encoded to fit into small table cells. Table 7-36 shows the codes that are used for access types in this section.

Table 7-36 CLA_REGS Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
W1S	W 1S	Write 1 to set
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

7.8.4.1 MVECT1 Register (Offset = 0h) [Reset = 0000h]

MVECT1 is shown in Figure 7-10 and described in Table 7-37.

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Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .

Figure 7-10 MVECT1 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-37 MVECT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.2 MVECT2 Register (Offset = 1h) [Reset = 0000h]

MVECT2 is shown in Figure 7-11 and described in Table 7-38.

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Figure 7-11 MVECT2 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-38 MVECT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.3 MVECT3 Register (Offset = 2h) [Reset = 0000h]

MVECT3 is shown in Figure 7-12 and described in Table 7-39.

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Figure 7-12 MVECT3 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-39 MVECT3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.4 MVECT4 Register (Offset = 3h) [Reset = 0000h]

MVECT4 is shown in Figure 7-13 and described in Table 7-40.

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Figure 7-13 MVECT4 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-40 MVECT4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.5 MVECT5 Register (Offset = 4h) [Reset = 0000h]

MVECT5 is shown in Figure 7-14 and described in Table 7-41.

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Figure 7-14 MVECT5 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-41 MVECT5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.6 MVECT6 Register (Offset = 5h) [Reset = 0000h]

MVECT6 is shown in Figure 7-15 and described in Table 7-42.

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Figure 7-15 MVECT6 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-42 MVECT6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.7 MVECT7 Register (Offset = 6h) [Reset = 0000h]

MVECT7 is shown in Figure 7-16 and described in Table 7-43.

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Figure 7-16 MVECT7 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-43 MVECT7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.8 MVECT8 Register (Offset = 7h) [Reset = 0000h]

MVECT8 is shown in Figure 7-17 and described in Table 7-44.

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Figure 7-17 MVECT8 Register

15	14	13	12	11	10	9	8
MVECT
R/W-0h

7	6	5	4	3	2	1	0
MVECT
R/W-0h

Table 7-44 MVECT8 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MVECT	R/W	0h	MPC Start Address: These bits specify the start address for the given interrupt (task). The address range of the CLA with a 16-bit MVECT is 64Kx16 words or 32K CLA instructions. There is one MVECT register per interrupt (task). Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Reset type: SYSRSn

7.8.4.9 MCTL Register (Offset = 10h) [Reset = 0000h]

MCTL is shown in Figure 7-18 and described in Table 7-45.

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Control Register

Figure 7-18 MCTL Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					IACKE	SOFTRESET	HARDRESET
R-0h					R/W-0h	R-0/W1S-0h	R-0/W1S-0h

Table 7-45 MCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2	IACKE	R/W	0h	IACK Operation Enable Bit: Writing a '1' to this bit will enable the IACK operation for setting the MIFR bits in the same manner as the MIFRC register (write of '1' will set respective MIFR bit). At reset, this feature is disabled. This feature enables the C28 CPU to efficiently trigger a task. Note: IACK operation should ignore EALLOW status of C28 core when accessing the MIFRC register. Reset type: SYSRSn 0h (R/W) = The CLA ignores the IACK instruction. (default) 1h (R/W) = Enable the main CPU to use the IACK #16bit instruction to set MIFR bits in the same manner as writing to the MIFRC register. Each bit in the operand, #16bit, corresponds to a bit in the MIFRC register. Using IACK has the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger a CLA task through software. Examples IACK #0x0001 Write a 1 to MIFRC bit 0 to force task 1 IACK #0x0003 Write a 1 to MIFRC bit 0 and 1 to force task 1 and task 2
1	SOFTRESET	R-0/W1S	0h	Soft Reset Bit: Writing a '1' to this bit will stop a current task, clear the RUN flag and also clear all bits in the MIER register. Writes of '0' are ignored and reads always return a '0'. Note: After issuing SOFTRESET command, user should wait at least 1 clock cycle before attempting to write to MIER register. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 are ignored. 1h (R/W) = Writing a 1 will cause a soft reset of the CLA. This will stop the current task, clear the MIRUN flag and clear all bits in the MIER register. After a soft reset you must wait at least 1 SYSCLKOUT cycle before reconfiguring the MIER bits. If these two operations are done back-to-back then the MIER bits will not get set.
0	HARDRESET	R-0/W1S	0h	Hard Reset Bit: Writing a '1' to this bit will cause a HARD reset on the CLA. The behavior of a HARD reset is the same as a system reset SYSRSn on the CLA. Writes of '0' are ignored and reads always return a '0'. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 are ignored. 1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will set all CLA registers to their default state.

7.8.4.10 _MVECTBGRNDACTIVE Register (Offset = 1Bh) [Reset = 0000h]

_MVECTBGRNDACTIVE is shown in Figure 7-19 and described in Table 7-46.

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Gives the current interrupted MPC value of the background task, if the background task was running and interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.

Figure 7-19 _MVECTBGRNDACTIVE Register

15	14	13	12	11	10	9	8
i16
R-0h

7	6	5	4	3	2	1	0
i16
R-0h

Table 7-46 _MVECTBGRNDACTIVE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	i16	R	0h	Gives the current interrupted MPC value of the background task, if the background task was running and interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0. Reset type: SYSRSn

7.8.4.11 SOFTINTEN Register (Offset = 1Ch) [Reset = 0000h]

SOFTINTEN is shown in Figure 7-20 and described in Table 7-47.

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Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register. SOFTINTFRC register can only be written from CLA. Only reads are allowed from CPU. Writes are not allowed from CPU.

Figure 7-20 SOFTINTEN Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
TASK8	TASK7	TASK6	TASK5	TASK4	TASK3	TASK2	TASK1
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-47 SOFTINTEN Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R/W	0h	Reserved
7	TASK8	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn
6	TASK7	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn
5	TASK6	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn
4	TASK5	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn
3	TASK4	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn
2	TASK3	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn
1	TASK2	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn
0	TASK1	R/W	0h	0: End-Of-Task Interrupt is fired for the respective task 1: Enable Software Interrupt for the respective task. End-of-Task interrupt is not sent to CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. Reset type: SYSRSn

7.8.4.12 _MSTSBGRND Register (Offset = 1Dh) [Reset = 0000h]

_MSTSBGRND is shown in Figure 7-21 and described in Table 7-48.

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Status bits for the backgrondtask.

Figure 7-21 _MSTSBGRND Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED					BGOVF	_BGINTM	RUN
R/W-0h					R/W1C-0h	R-0h	R-0h

Table 7-48 _MSTSBGRND Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R/W	0h	Reserved
2	BGOVF	R/W1C	0h	Value of 1 indicates a hardware trigger (which is enabled) occurred while the MCTLBGRND.BGSTART bit is set. Writing a value of 1 to this bit clears the BGOVF bit. Write of 0 has no effect, Value of 0 indicates the background task trigger did not result in a overflow. Reset type: SYSRSn
1	_BGINTM	R	0h	Value of 1 indicates that backgroiund task will not be interrupted. This bit is set when MSETC _BGINTM bit is executed. Value of 0 indicates that background task can be interrupted. Reset type: SYSRSn
0	RUN	R	0h	Value of 1 indicates that background task is running. Value of 0 indicates that background task is not running. Reset type: SYSRSn

7.8.4.13 _MCTLBGRND Register (Offset = 1Eh) [Reset = 0000h]

_MCTLBGRND is shown in Figure 7-22 and described in Table 7-49.

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Holds the configuration bits to start the background task, enable hardware trigger.

Figure 7-22 _MCTLBGRND Register

15	14	13	12	11	10	9	8
BGEN	RESERVED
R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED						TRIGEN	BGSTART
R/W-0h						R/W-0h	R/W1S-0h

Table 7-49 _MCTLBGRND Register Field Descriptions

Bit	Field	Type	Reset	Description
15	BGEN	R/W	0h	0 Background task is disabled, BGSTART will not be set either in a hardware trigger or by writing 1 to BGSTART bit. 1 Background task is enabled and MIER[INT8] will be cleared, preventing task 8 from triggering. Reset type: SYSRSn
14-2	RESERVED	R/W	0h	Reserved
1	TRIGEN	R/W	0h	Hardware trigger enable for the background task. 1 Hardware trigger is enabled. 0 Hardware trigger is disabled. Note: Trigger source for the background task will be the same as that for task 8 Reset type: SYSRSn
0	BGSTART	R/W1S	0h	Value of 1 will start the background task, provided there are no other pending tasks. - Value of 0 has no effect if the background task has not started. - This bit is also set by hardware, if MCTLBGRND.TRIGEN = 1 and a hardware trigger occurs. - This bit is cleared by hardware when a MSTOP instruction occurs in the background task - If the background task is running and this bit is cleared, it will not have any effect on the task execution. Reset type: SYSRSn

7.8.4.14 _MVECTBGRND Register (Offset = 1Fh) [Reset = 0000h]

_MVECTBGRND is shown in Figure 7-23 and described in Table 7-50.

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These bits specify the start address for the background task . The value in this register is forced into the MPC register when the background task starts.

Figure 7-23 _MVECTBGRND Register

15	14	13	12	11	10	9	8
i16
R/W-0h

7	6	5	4	3	2	1	0
i16
R/W-0h

Table 7-50 _MVECTBGRND Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	i16	R/W	0h	MPC Start Address: These bits specify the start address for the background task . The value in this register is forced into the MPC register, when the background task starts. Reset type: SYSRSn

7.8.4.15 MIFR Register (Offset = 20h) [Reset = 0000h]

MIFR is shown in Figure 7-24 and described in Table 7-51.

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Each bit in the interrupt flag register corresponds to a CLA task. The corresponding bit is automatically set
when the task request is received from the peripheral interrupt. The bit can also be set by the main CPU
writing to the MIFRC register or using the IACK instruction to start the task. To use the IACK instruction to
begin a task first enable this feature in the MCTL register. If the bit is already set when a new peripheral
interrupt is received, then the corresponding overflow bit will be set in the MIOVF register.
The corresponding MIFR bit is automatically cleared when the task begins execution. This will occur if the
interrupt is enabled in the MIER register and no other higher priority task is pending. The bits can also be
cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored.

Figure 7-24 MIFR Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
INT8	INT7	INT6	INT5	INT4	INT3	INT2	INT1
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-51 MIFR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	INT8	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 8 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 8 interrupt has been received and is pending execution
6	INT7	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 7 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 7 interrupt has been received and is pending execution
5	INT6	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 6 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 6 interrupt has been received and is pending execution
4	INT5	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 5 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 5 interrupt has been received and is pending execution
3	INT4	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 4 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 4 interrupt has been received and is pending execution
2	INT3	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 3 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 3 interrupt has been received and is pending execution
1	INT2	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 2 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 2 interrupt has been received and is pending execution
0	INT1	R	0h	These bits, when set to '1', indicate a valid peripheral interrupt has been latched by the CLA. Writes to this register are ignored. The IFR flag bit is automatically cleared if the respective interrupt is enabled in the MIER register and the respective task starts running. If a new peripheral interrupt attempts to set the bit to '1' while on the same cycle the task tries to clear it, then the peripheral interrupt will have priority. The IFR flag bits can also be set and cleared by the MIFRC and MICLR registers. If the MIFRC register is trying to set the respective bit while a new task tries to clear it, then the MIFRC event has priority. If the MICLR register is trying to clear the respective bit and a peripheral interrupt occurs on the same cycle, then the peripheral interrupt has priority. The respective overflow flag in the MIOVF register will not be set under this condition. Reset type: SYSRSn 0h (R/W) = TASK_FLAG_DISABLE Task 1 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 1 interrupt has been received and is pending execution

7.8.4.16 MIOVF Register (Offset = 21h) [Reset = 0000h]

MIOVF is shown in Figure 7-25 and described in Table 7-52.

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Each bit in the overflow flag register corresponds to a CLA task. The bit is set when an interrupt overflow
event has occurred for the specific task. An overflow event occurs when the MIFR register bit is already
set when a new interrupt is received from a peripheral source. The MIOVF bits are only affected by
peripheral interrupt events. They do not respond to a task request by the main CPU IACK instruction or by
directly setting MIFR bits. The overflow flag will remain latched and can only be cleared by writing to the
overflow flag clear (MICLROVF) register. Writes to the MIOVF register are ignored.

Figure 7-25 MIOVF Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
INT8	INT7	INT6	INT5	INT4	INT3	INT2	INT1
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-52 MIOVF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	INT8	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 8 interrupt overflow has not occurred (default) 1h (R/W) = A task 8 interrupt overflow has occurred
6	INT7	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 7 interrupt overflow has not occurred (default) 1h (R/W) = A task 7 interrupt overflow has occurred
5	INT6	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 6 interrupt overflow has not occurred (default) 1h (R/W) = A task 6 interrupt overflow has occurred
4	INT5	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 5 interrupt overflow has not occurred (default) 1h (R/W) = A task 5 interrupt overflow has occurred
3	INT4	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 4 interrupt overflow has not occurred (default) 1h (R/W) = A task 4 interrupt overflow has occurred
2	INT3	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 3 interrupt overflow has not occurred (default) 1h (R/W) = A task 3 interrupt overflow has occurred
1	INT2	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 2 interrupt overflow has not occurred (default) 1h (R/W) = A task 2 interrupt overflow has occurred
0	INT1	R	0h	These bits, when set to '1', indicate an interrupt overflow event occurred. Such an event occurs when the IFR bit is already set. An overflow event remains latched and respective bits can only be cleared by writing to the MICLROVF register. If the MIFR bit is being cleared by a new task on the same cycle as a new peripheral interrupt occurs, the overflow flag will not be affected and the respective MIFR bit will be set. If the MIOVF bit is being cleared by the MICLROVF register on the same cycle as the overflow bit is being set by hardware, then the hardware will have priority. Notes: [1] The MIOVF bits are only affected by peripheral interrupt events. Forcing an interrupt using the MIFRC or IACK operation will not set the overflow flag even if the MIFR bit is set. Reset type: SYSRSn 0h (R/W) = A task 1 interrupt overflow has not occurred (default) 1h (R/W) = A task 1 interrupt overflow has occurred

7.8.4.17 MIFRC Register (Offset = 22h) [Reset = 0000h]

MIFRC is shown in Figure 7-26 and described in Table 7-53.

Return to the Summary Table.

The interrupt force register can be used by the main CPU to start tasks through software. Writing a 1 to a
MIFRC bit will set the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0. The IACK #16bit operation can also be used to start tasks and has the same effect as the
MIFRC register. To enable IACK to set MIFR bits you must first set the MCTL[IACKE] bit. Using IACK has
the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger
CLA tasks through software.

Figure 7-26 MIFRC Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
INT8	INT7	INT6	INT5	INT4	INT3	INT2	INT1
R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

Table 7-53 MIFRC Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	INT8	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 8 interrupt
6	INT7	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 7 interrupt
5	INT6	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 6 interrupt
4	INT5	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 5 interrupt
3	INT4	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 4 interrupt
2	INT3	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 3 interrupt
1	INT2	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 2 interrupt
0	INT1	R-0/W1S	0h	Writing a '1' to any of the bits will set the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 1 interrupt

7.8.4.18 MICLR Register (Offset = 23h) [Reset = 0000h]

MICLR is shown in Figure 7-27 and described in Table 7-54.

Return to the Summary Table.

Normally bits in the MIFR register are automatically cleared when a task begins. The interrupt flag clear
register can be used to instead manually clear bits in the interrupt flag (MIFR) register. Writing a 1 to a
MICLR bit will clear the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0.

Figure 7-27 MICLR Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
INT8	INT7	INT6	INT5	INT4	INT3	INT2	INT1
R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

Table 7-54 MICLR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	INT8	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 8 interrupt flag
6	INT7	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 7 interrupt flag
5	INT6	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 6 interrupt flag
4	INT5	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 5 interrupt flag
3	INT4	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 4 interrupt flag
2	INT3	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 3 interrupt flag
1	INT2	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 2 interrupt flag
0	INT1	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIFR bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIFR register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 1 interrupt flag

7.8.4.19 MICLROVF Register (Offset = 24h) [Reset = 0000h]

MICLROVF is shown in Figure 7-28 and described in Table 7-55.

Return to the Summary Table.

Overflow flag bits in the MIOVF register are latched until manually cleared using the MICLROVF register.
Writing a 1 to a MICLROVF bit will clear the corresponding bit in the MIOVF register. Writes of 0 are
ignored and reads always return 0.

Figure 7-28 MICLROVF Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
INT8	INT7	INT6	INT5	INT4	INT3	INT2	INT1
R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

Table 7-55 MICLROVF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	INT8	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 8 interrupt overflow flag
6	INT7	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 7 interrupt overflow flag
5	INT6	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 6 interrupt overflow flag
4	INT5	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 5 interrupt overflow flag
3	INT4	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag
2	INT3	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 3 interrupt overflow flag
1	INT2	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 2 interrupt overflow flag
0	INT1	R-0/W1S	0h	Writing a '1' to any of the bits will clear the corresponding MIOVF bit. Writes of '0' are ignored. Reads always return 0. Notes: [1] Refer to MIOVF register description for handling of boundary conditions. Reset type: SYSRSn 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag

7.8.4.20 MIER Register (Offset = 25h) [Reset = 0000h]

MIER is shown in Figure 7-29 and described in Table 7-56.

Return to the Summary Table.

Setting the bits in the interrupt enable register (MIER) allow an incoming interrupt or main CPU software to
start the corresponding CLA task. Writing a 0 will block the task, but the interrupt request will still be
latched in the flag register (MIFLG). Setting the MIER register bit to 0 while the corresponding task is
executing will have no effect on the task. The task will continue to run until it hits the MSTOP instruction.
When a soft reset is issued, the MIER bits are cleared. There should always be at least a 1 SYSCLKOUT
delay between issuing the soft reset and reconfiguring the MIER bits.

Figure 7-29 MIER Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
INT8	INT7	INT6	INT5	INT4	INT3	INT2	INT1
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-56 MIER Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	INT8	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 8 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 8 interrupt is enabled
6	INT7	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 7 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 7 interrupt is enabled
5	INT6	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 6 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 6 interrupt is enabled
4	INT5	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 5 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 5 interrupt is enabled
3	INT4	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 4 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 4 interrupt is enabled
2	INT3	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 3 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 3 interrupt is enabled
1	INT2	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 2 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 2 interrupt is enabled
0	INT1	R/W	0h	Setting any of the bits to '1' enables the corresponding interrupt from triggering a corresponding CLA task. Writing a '0' blocks the interrupt, but the interrupt can still be latched by the MIFR register. When an interrupt is enabled and the corresponding MIFR bit is set to '1', the CLA will start executing the corresponding task and automatically clear the corresponding MIFR bit. Interrupts are be serviced in normal priority order. Notes: [1] If a task is currently executing and the corresponding MIER bit is cleared to '0', it will have no effect on the task. The task will run until it hits the STOP instruction. Reset type: SYSRSn 0h (R/W) = TASK_INT_DISABLE Task 1 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 1 interrupt is enabled

7.8.4.21 MIRUN Register (Offset = 26h) [Reset = 0000h]

MIRUN is shown in Figure 7-30 and described in Table 7-57.

Return to the Summary Table.

The interrupt run status register (MIRUN) indicates which task is currently executing. Only one MIRUN bit
will ever be set to a 1 at any given time. The bit is automatically cleared when the task competes and the
respective interrupt is fed to the peripheral interrupt expansion (PIE) block of the device. This lets the main
CPU know when a task has completed. The main CPU can stop a currently running task by writing to the
MCTL[SOFTRESET] bit. This will clear the MIRUN flag and stop the task. In this case no interrupt will be
generated to the PIE.

Figure 7-30 MIRUN Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
INT8	INT7	INT6	INT5	INT4	INT3	INT2	INT1
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-57 MIRUN Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	INT8	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 8 is not executing (default) 1h (R/W) = Task 8 is executing
6	INT7	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 7 is not executing (default) 1h (R/W) = Task 7 is executing
5	INT6	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 6 is not executing (default) 1h (R/W) = Task 6 is executing
4	INT5	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 5 is not executing (default) 1h (R/W) = Task 5 is executing
3	INT4	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 4 is not executing (default) 1h (R/W) = Task 4 is executing
2	INT3	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 3 is not executing (default) 1h (R/W) = Task 3 is executing
1	INT2	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 2 is not executing (default) 1h (R/W) = Task 2 is executing
0	INT1	R	0h	These bits indicate which task is currently active. Only one bit can be set to '1' at any one time. The bit is automatically cleared to '0' when the task completes and the respective CLAINTxn line is toggled to indicate task completion. The CLAINTxn interrupt line can be fed to the PIE of the CPU so the CPU knows when a task has completed. A currently running task can be stopped by a SOFTRESET. The RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt is generated. Reset type: SYSRSn 0h (R/W) = Task 1 is not executing (default) 1h (R/W) = Task 1 is executing

7.8.4.22 _MPC Register (Offset = 28h) [Reset = 0000h]

_MPC is shown in Figure 7-31 and described in Table 7-58.

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CLA Program Counter

Figure 7-31 _MPC Register

15	14	13	12	11	10	9	8
_MPC
R-0h

7	6	5	4	3	2	1	0
_MPC
R-0h

Table 7-58 _MPC Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	_MPC	R	0h	Program Counter: The PC value is initialized by the appropriate MVECTx register when an interrupt (task) is serviced. The MPC register address 16-bits and not 32-bits. Hence the address range of the CLA with a 16-bit MPC is 64Kx16 words or 32K CLA instructions. Notes: [1] To be consistent with C28 core implementation, the PC value points to the instruction in D2 stage of pipeline. [2] After a STOP operation, and with no other task pending, the PC will remain pointing to the STOP operation. Reset type: SYSRSn

7.8.4.23 _MAR0 Register (Offset = 2Ah) [Reset = 0000h]

_MAR0 is shown in Figure 7-32 and described in Table 7-59.

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CLA Auxiliary Register 0

Figure 7-32 _MAR0 Register

15	14	13	12	11	10	9	8
_MAR0
R-0h

7	6	5	4	3	2	1	0
_MAR0
R-0h

Table 7-59 _MAR0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	_MAR0	R	0h	CLA Auxillary Register 0 Reset type: SYSRSn

7.8.4.24 _MAR1 Register (Offset = 2Bh) [Reset = 0000h]

_MAR1 is shown in Figure 7-33 and described in Table 7-60.

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CLA Auxiliary Register 1

Figure 7-33 _MAR1 Register

15	14	13	12	11	10	9	8
_MAR1
R-0h

7	6	5	4	3	2	1	0
_MAR1
R-0h

Table 7-60 _MAR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	_MAR1	R	0h	CLA Auxillary Register 1 Reset type: SYSRSn

7.8.4.25 _MSTF Register (Offset = 2Eh) [Reset = 00000000h]

_MSTF is shown in Figure 7-34 and described in Table 7-61.

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The CLA status register (MSTF) reflects the results of different operations. These are the basic rules for
the flags:
- Zero and negative flags are cleared or set based on:
- floating-point moves to registers
- the result of compare, minimum, maximum, negative and absolute value operations
- the integer result of operations such as MMOV16, MAND32, MOR32, MXOR32, MCMP32,
MASR32, MLSR32
- Overflow and underflow flags are set by floating-point math instructions such as multiply, add, subtract
and 1/x. These flags may also be connected to the peripheral interrupt expansion (PIE) block on your
device. This can be useful for debugging underflow and overflow conditions within an application.

Figure 7-34 _MSTF Register

31	30	29	28	27	26	25	24
RESERVED				_RPC
R-0h				R-0h

23	22	21	20	19	18	17	16
_RPC
R-0h

15	14	13	12	11	10	9	8
_RPC				MEALLOW	RESERVED	RNDF32	RESERVED
R-0h				R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	TF	RESERVED		ZF	NF	LUF	LVF
R-0h	R-0h	R-0h		R-0h	R-0h	R-0h	R-0h

Table 7-61 _MSTF Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-12	_RPC	R	0h	Return program counter The _RPC is used to save and restore the MPC address by the MCCNDD and MRCNDD operations Reset type: SYSRSn
11	MEALLOW	R	0h	MEALLOW Status This bit enables and disables CLA write access to EALLOW protected registers This is independent of the state of the EALLOW bit in the main CPU status register This status bit can be saved and restored by the MMOV32 STF, mem32 instruction Reset type: SYSRSn 0h (R/W) = The CLA cannot write to EALLOW protected registers. This bit is cleared by the CLA instruction, MEDIS. 1h (R/W) = The CLA is allowed to write to EALLOW protected registers. This bit is set by the CLA instruction, MEALLOW.
10	RESERVED	R	0h	Reserved
9	RNDF32	R	0h	Round 32-bit Floating-Point Mode Use the MSETFLG and MMOV32 MSTF, mem32 instructions to change the rounding mode Reset type: SYSRSn 0h (R/W) = If this bit is zero, the MMPYF32, MADDF32 and MSUBF32 instructions will round to zero (truncate). 1h (R/W) = If this bit is one, the MMPYF32, MADDF32 and MSUBF32 instructions will round to the nearest even value.
8-7	RESERVED	R	0h	Reserved
6	TF	R	0h	Test Flag The MTESTTF instruction can modify this flag based on the condition tested The MSETFLG and MMOV32 MSTF, mem32 instructions can also be used to modify this flag Reset type: SYSRSn 0h (R/W) = The condition tested with the MTESTTF instruction is false. 1h (R/W) = The condition tested with the MTESTTF instruction is true.
5-4	RESERVED	R	0h	Reserved
3	ZF	R	0h	Zero Flag - Instructions that modify this flag based on the floating-point value stored in the destination register: MMOV32, MMOVD32, MABSF32, MNEGF32 - Instructions that modify this flag based on the floating-point result of the operation: MCMPF32, MMAXF32, and MMINF32 - Instructions that modify this flag based on the integer result of the operation: MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32, MLSR32 and MLSL32 The MSETFLG and MMOV32 MSTF, mem32 instructions can also be used to modify this flag Reset type: SYSRSn 0h (R/W) = The value is not zero 1h (R/W) = The value is zero
2	NF	R	0h	Negative Flag - Instructions that modify this flag based on the floating-point value stored in the destination register: MMOV32, MMOVD32, MABSF32, MNEGF32 - Instructions that modify this flag based on the floating-point result of the operation: MCMPF32, MMAXF32, and MMINF32 - Instructions that modify this flag based on the integer result of the operation: MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32, MLSR32 and MLSL32 The MSETFLG and MMOV32 MSTF, mem32 instructions can also be used to modify this flag Reset type: SYSRSn 0h (R/W) = The value is not negative 1h (R/W) = The value is negative
1	LUF	R	0h	Latched Underflow Flag The following instructions will set this flag to 1 if an underflow occurs: MMPYF32, MADDF32, MSUBF32, MMACF32, MEINVF32, MEISQRTF32 The MSETFLG and MMOV32 MSTF, mem32 instructions can also be used to modify this flag Reset type: SYSRSn 0h (R/W) = An underflow condition has not been latched 1h (R/W) = An underflow condition has been latched
0	LVF	R	0h	Latched Overflow Flag The following instructions will set this flag to 1 if an overflow occurs: MMPYF32, MADDF32, MSUBF32, MMACF32, MEINVF32, MEISQRTF32 The MSETFLG and MMOV32 MSTF, mem32 instructions can also be used to modify this flag Reset type: SYSRSn 0h (R/W) = An overflow condition has not been latched 1h (R/W) = An overflow condition has been latched

7.8.4.26 _MR0 Register (Offset = 30h) [Reset = 00000000h]

_MR0 is shown in Figure 7-35 and described in Table 7-62.

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CLA Floating-Point Result Register 0

Figure 7-35 _MR0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
i32
R-0h

Table 7-62 _MR0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	i32	R	0h	CLA Result Register 0 Reset type: SYSRSn

7.8.4.27 _MR1 Register (Offset = 34h) [Reset = 00000000h]

_MR1 is shown in Figure 7-36 and described in Table 7-63.

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CLA Floating-Point Result Register 1

Figure 7-36 _MR1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
i32
R-0h

Table 7-63 _MR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	i32	R	0h	CLA Result Register 1 Reset type: SYSRSn

7.8.4.28 _MR2 Register (Offset = 38h) [Reset = 00000000h]

_MR2 is shown in Figure 7-37 and described in Table 7-64.

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CLA Floating-Point Result Register 2

Figure 7-37 _MR2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
i32
R-0h

Table 7-64 _MR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	i32	R	0h	CLA Result Register 2 Reset type: SYSRSn

7.8.4.29 _MR3 Register (Offset = 3Ch) [Reset = 00000000h]

_MR3 is shown in Figure 7-38 and described in Table 7-65.

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CLA Floating-Point Result Register 3

Figure 7-38 _MR3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
i32
R-0h

Table 7-65 _MR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	i32	R	0h	CLA Result Register 3 Reset type: SYSRSn

7.8.4.30 _MPSACTL Register (Offset = 42h) [Reset = 0000h]

_MPSACTL is shown in Figure 7-39 and described in Table 7-66.

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PSA Control Register

Figure 7-39 _MPSACTL Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
MPSA2CFG		MPSA2CLEAR	MPSA1CLEAR	MDWDBCYC	MDWDBSTART	MPABCYC	MPABSTART
R/W-0h		R-0/W1S-0h	R-0/W1S-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-66 _MPSACTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-6	MPSA2CFG	R/W	0h	CLA PSA2 Polynomial Configuration Bits: These bits configure the type of polynomial used for PSA2. The polynomials chosen are commonly used in the industry: Mode Polynomial Type 0,0 PSA 0,1 CRC32 1,0 CRC16 1,1 CRC16-CCITT Note: [1] Polynomial configuration should be performed when PSA2 is stopped. Reset type: SYSRSn
5	MPSA2CLEAR	R-0/W1S	0h	CLA PSA2 Clear Bit: Writing of '1' will clear contents of PSA2 register. Writes of '0' are ignored. Always reads back a '0' Note: Clearing operation should be performed when PSA2 is stopped. Reset type: SYSRSn
4	MPSA1CLEAR	R-0/W1S	0h	CLA PSA1 Clear Bit: Writing of '1' will clear contents of PSA1 register. Writes of '0' are ignored. Always reads back a '0' Note: Clearing operation should be performed when PSA1 is stopped. Reset type: SYSRSn
3	MDWDBCYC	R/W	0h	CLA Data Write Data Bus PSA2 Cycle or Event Based Bit: 0 PSA2 calculated on every cycle 1 PSA2 calculated on every bus event Reset type: SYSRSn
2	MDWDBSTART	R/W	0h	CLA Data Write Data Bus PSA2 Start/Stop Bit: 0 PSA2 stopped 1 PSA2 start Reset type: SYSRSn
1	MPABCYC	R/W	0h	CLA Program Address Bus PSA1 Cycle/Event Based Bit: 0 PSA1 calculated on every cycle 1 PSA1 calculated on every bus event Reset type: SYSRSn
0	MPABSTART	R/W	0h	CLA Program Address Bus PSA1 Start/Stop Bit: 0 PSA1 stopped 1 PSA1 start Reset type: SYSRSn

7.8.4.31 _MPSA1 Register (Offset = 44h) [Reset = 00000000h]

_MPSA1 is shown in Figure 7-40 and described in Table 7-67.

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PSA1 Register

Figure 7-40 _MPSA1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
i32
R/W-0h

Table 7-67 _MPSA1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	i32	R/W	0h	PSA1 Value: Reading this register gives the current PSA1 value. The value can be read at any time. Writes to this register are allowed to initialize the PSA1 to a known value. Writes to this register should only be made when PSA1 is stopped. Register value is cleared to zero by reset or by writing to the MPSA1CLEAR bit in the MPSACTL register. Reset type: SYSRSn

7.8.4.32 _MPSA2 Register (Offset = 46h) [Reset = 00000000h]

_MPSA2 is shown in Figure 7-41 and described in Table 7-68.

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PSA2 Register

Figure 7-41 _MPSA2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
i32
R/W-0h

Table 7-68 _MPSA2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	i32	R/W	0h	PSA2 Value: Reading this register gives the current PSA2 value. The value can be read at any time. Writes to this register are allowed to initialize the PSA2 to a known value. Writes to this register should only be made when PSA2 is stopped. Register value is cleared to zero by reset or by writing to the MPSA2CLEAR bit in the MPSACTL register. Reset type: SYSRSn