SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 34-28 lists the memory-mapped registers for the EPG_MUX_REGS registers. All register offset addresses not listed in Table 34-28 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | EPGMXSEL0 | EPG Mux select register 0 | Go | |
Ch | EPGMXSELLOCK | EPG Mux select register lock | Go | |
Eh | EPGMXSELCOMMIT | EPG Mux select register commit | Go |
Complex bit access types are encoded to fit into small table cells. Table 34-29 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
EPGMXSEL0 is shown in Figure 34-28 and described in Table 34-30.
Return to the Summary Table.
EPG Mux select register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SEL31 | SEL30 | SEL29 | SEL28 | SEL27 | SEL26 | SEL25 | SEL24 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SEL23 | SEL22 | SEL21 | SEL20 | SEL19 | SEL18 | SEL17 | SEL16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEL15 | SEL14 | SEL13 | SEL12 | SEL11 | SEL10 | SEL9 | SEL8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL7 | SEL6 | SEL5 | SEL4 | SEL3 | SEL2 | SEL1 | SEL0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SEL31 | R/W | 0h | 0: DATAIN[31] is selected 1: EPGOUT[7] is selected Reset type: SYSRSn |
30 | SEL30 | R/W | 0h | 0: DATAIN[30] is selected 1: EPGOUT[6] is selected Reset type: SYSRSn |
29 | SEL29 | R/W | 0h | 0: DATAIN[29] is selected 1: EPGOUT[5] is selected Reset type: SYSRSn |
28 | SEL28 | R/W | 0h | 0: DATAIN[28] is selected 1: EPGOUT[4] is selected Reset type: SYSRSn |
27 | SEL27 | R/W | 0h | 0: DATAIN[27] is selected 1: EPGOUT[3] is selected Reset type: SYSRSn |
26 | SEL26 | R/W | 0h | 0: DATAIN[26] is selected 1: EPGOUT[2] is selected Reset type: SYSRSn |
25 | SEL25 | R/W | 0h | 0: DATAIN[25] is selected 1: EPGOUT[1] is selected Reset type: SYSRSn |
24 | SEL24 | R/W | 0h | 0: DATAIN[24] is selected 1: EPGOUT[0] is selected Reset type: SYSRSn |
23 | SEL23 | R/W | 0h | 0: DATAIN[23] is selected 1: EPGOUT[7] is selected Reset type: SYSRSn |
22 | SEL22 | R/W | 0h | 0: DATAIN[22] is selected 1: EPGOUT[6] is selected Reset type: SYSRSn |
21 | SEL21 | R/W | 0h | 0: DATAIN[21] is selected 1: EPGOUT[5] is selected Reset type: SYSRSn |
20 | SEL20 | R/W | 0h | 0: DATAIN[20] is selected 1: EPGOUT[4] is selected Reset type: SYSRSn |
19 | SEL19 | R/W | 0h | 0: DATAIN[19] is selected 1: EPGOUT[3] is selected Reset type: SYSRSn |
18 | SEL18 | R/W | 0h | 0: DATAIN[18] is selected 1: EPGOUT[2] is selected Reset type: SYSRSn |
17 | SEL17 | R/W | 0h | 0: DATAIN[17] is selected 1: EPGOUT[1] is selected Reset type: SYSRSn |
16 | SEL16 | R/W | 0h | 0: DATAIN[16] is selected 1: EPGOUT[0] is selected Reset type: SYSRSn |
15 | SEL15 | R/W | 0h | 0: DATAIN[15] is selected 1: EPGOUT[7] is selected Reset type: SYSRSn |
14 | SEL14 | R/W | 0h | 0: DATAIN[14] is selected 1: EPGOUT[6] is selected Reset type: SYSRSn |
13 | SEL13 | R/W | 0h | 0: DATAIN[13] is selected 1: EPGOUT[5] is selected Reset type: SYSRSn |
12 | SEL12 | R/W | 0h | 0: DATAIN[12] is selected 1: EPGOUT[4] is selected Reset type: SYSRSn |
11 | SEL11 | R/W | 0h | 0: DATAIN[11] is selected 1: EPGOUT[3] is selected Reset type: SYSRSn |
10 | SEL10 | R/W | 0h | 0: DATAIN[10] is selected 1: EPGOUT[2] is selected Reset type: SYSRSn |
9 | SEL9 | R/W | 0h | 0: DATAIN[9] is selected 1: EPGOUT[1] is selected Reset type: SYSRSn |
8 | SEL8 | R/W | 0h | 0: DATAIN[8] is selected 1: EPGOUT[0] is selected Reset type: SYSRSn |
7 | SEL7 | R/W | 0h | 0: DATAIN[7] is selected 1: EPGOUT[7] is selected Reset type: SYSRSn |
6 | SEL6 | R/W | 0h | 0: DATAIN[6] is selected 1: EPGOUT[6] is selected Reset type: SYSRSn |
5 | SEL5 | R/W | 0h | 0: DATAIN[5] is selected 1: EPGOUT[5] is selected Reset type: SYSRSn |
4 | SEL4 | R/W | 0h | 0: DATAIN[4] is selected 1: EPGOUT[4] is selected Reset type: SYSRSn |
3 | SEL3 | R/W | 0h | 0: DATAIN[3] is selected 1: EPGOUT[3] is selected Reset type: SYSRSn |
2 | SEL2 | R/W | 0h | 0: DATAIN[2] is selected 1: EPGOUT[2] is selected Reset type: SYSRSn |
1 | SEL1 | R/W | 0h | 0: DATAIN[1] is selected 1: EPGOUT[1] is selected Reset type: SYSRSn |
0 | SEL0 | R/W | 0h | 0: DATAIN[0] is selected 1: EPGOUT[0] is selected Reset type: SYSRSn |
EPGMXSELLOCK is shown in Figure 34-29 and described in Table 34-31.
Return to the Summary Table.
EPG Mux select register lock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | EPGMXSEL0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | EPGMXSEL0 | R/W | 0h | 0: Writes to EPGMXSEL0 registers are allowed. 1: Writes to EPGMXSEL0 registers are not allowed. Reset type: SYSRSn |
EPGMXSELCOMMIT is shown in Figure 34-30 and described in Table 34-32.
Return to the Summary Table.
EPG Mux select register commit
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | EPGMXSEL0 | |||||
R-0h | R/WSonce-0h | R/WSonce-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R/WSonce | 0h | Reserved |
0 | EPGMXSEL0 | R/WSonce | 0h | 0: Writes to EPGMXSELLOCK.EPGMXSEL12 field is allowed. 1: Writes to EPGMXSELLOCK.EPGMXSEL12 field is not allowed. Reset type: SYSRSn |