SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Branch Conditional Delayed
16BitDest | 16-bit destination if condition is true |
CNDF | Optional condition tested |
LSW: dest dest dest dest
MSW: 0111 1001 1000 cndf
If the specified condition is true, then branch by adding the signed 16BitDest value to the MPC value. Otherwise, continue without branching. If the address overflows, the address wraps around. Therefore, a value of "0xFFFE" puts the MPC back to the MBCNDD instruction.
Refer to the Pipeline section for important information regarding this instruction.
if (CNDF == TRUE) MPC += 16BitDest;
CNDF is one of the following conditions:
Encode(1) | CNDF | Description | MSTF Flags Tested |
---|---|---|---|
0000 | NEQ | Not equal to zero | ZF == 0 |
0001 | EQ | Equal to zero | ZF == 1 |
0010 | GT | Greater than zero | ZF == 0 AND NF == 0 |
0011 | GEQ | Greater than or equal to zero | NF == 0 |
0100 | LT | Less than zero | NF == 1 |
0101 | LEQ | Less than or equal to zero | ZF == 1 OR NF == 1 |
1010 | TF | Test flag set | TF == 1 |
1011 | NTF | Test flag not set | TF == 0 |
1100 | LU | Latched underflow | LUF == 1 |
1101 | LV | Latched overflow | LVF == 1 |
1110 | UNC | Unconditional | None |
1111 | UNCF(2) | Unconditional with flag modification | None |
The MBCNDD instruction is not allowed three instructions before or after a MBCNDD, MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more information.
This instruction does not modify flags in the MSTF register.
Flag | TF | ZF | NF | LUF | LVF |
---|---|---|---|---|---|
Modified | No | No | No | No | No |
The MBCNDD instruction alone is a single-cycle instruction. As shown in Table 7-12, 6 instruction slots are executed for each branch; 3 slots before the branch instruction (I2-I4) and 3 slots after the branch instruction (I5-I7). The total number of cycles for a branch taken or not taken depends on the usage of these slots. That is, the number of cycles depends on how many slots are filled with a MNOP as well as which slots are filled. The effective number of cycles for a branch can, therefore, range from 1 to 7 cycles. The number of cycles for a branch taken cannot be the same as for a branch not taken.
Referring to Table 7-12 and Table 7-13, the instructions before and after MBCNDD have the following properties:
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MBCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MBCNDD _Skip, NEQ ; Branch to Skip if not eqal to zero
; Three instructions after MBCNDD are always
; executed whether the branch is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....
_Skip:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
....
....
MSTOP
....
Instruction | F1 | F2 | D1 | D2 | R1 | R2 | E | W |
---|---|---|---|---|---|---|---|---|
I1 | I1 | |||||||
I2 | I2 | I1 | ||||||
I3 | I3 | I2 | I1 | |||||
I4 | I4 | I3 | I2 | I1 | ||||
MBCNDD | MBCNDD | I4 | I3 | I2 | I1 | |||
I5 | I5 | MBCNDD | I4 | I3 | I2 | I1 | ||
I6 | I6 | I5 | MBCNDD | I4 | I3 | I2 | I1 | |
I7 | I7 | I6 | I5 | MBCNDD | I4 | I3 | I2 | |
I8 | I8 | I7 | I6 | I5 | - | I4 | I3 | |
I9 | I9 | I8 | I7 | I6 | I5 | - | I4 | |
I10 | I10 | I9 | I8 | I7 | I6 | I5 | - | |
I10 | I9 | I8 | I7 | I6 | I5 | |||
I10 | I9 | I8 | I7 | I6 | ||||
I10 | I9 | I8 | I7 | |||||
I10 | I9 | I8 | ||||||
I10 | I9 | |||||||
I10 |
Instruction | F1 | F2 | D1 | D2 | R1 | R2 | E | W |
---|---|---|---|---|---|---|---|---|
I1 | I1 | |||||||
I2 | I2 | I1 | ||||||
I3 | I3 | I2 | I1 | |||||
I4 | I4 | I3 | I2 | I1 | ||||
MBCNDD | MBCNDD | I4 | I3 | I2 | I1 | |||
I5 | I5 | MBCNDD | I4 | I3 | I2 | I1 | ||
I6 | I6 | I5 | MBCNDD | I4 | I3 | I2 | I1 | |
I7 | I7 | I6 | I5 | MBCNDD | I4 | I3 | I2 | |
d1 | d1 | I7 | I6 | I5 | - | I4 | I3 | |
d2 | d2 | d1 | I7 | I6 | I5 | - | I4 | |
d3 | d3 | d2 | d1 | I7 | I6 | I5 | - | |
d3 | d2 | d1 | I7 | I6 | I5 | |||
d3 | d2 | d1 | I7 | I6 | ||||
d3 | d2 | d1 | I7 | |||||
d3 | d2 | d1 | ||||||
d3 | d2 | |||||||
d3 |
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task1:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @RampState ; Execute if (A) branch not taken
MMOVXI MR2, #RAMPMASK ; Execute if (A) branch not taken
MOR32 MR1, MR2 ; Execute if (A) branch not taken
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MCMPF32 MR0,#0.01 ; Affects flags for 2nd MBCNDD (B)
MNOP
MNOP
MNOP
MBCNDD Skip2,NEQ ; (B) If State != 0.01, go to Skip2
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @CoastState ; Execute if (B) branch not taken
MMOVXI MR2, #COASTMASK ; Execute if (B) branch not taken
MOR32 MR1, MR2 ; Execute if (B) branch not taken
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP
Skip2:
MMOV32 MR3, @SteadyState ; Executed if (B) branch taken
MMOVXI MR2, #STEADYMASK ; Executed if (B) branch taken
MOR32 MR3, MR2 ; Executed if (B) branch taken
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP
; This example is the same as Example 1, except
; the code is optimized to take advantage of delay slots
;
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MMOV32 MR3, @SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
Skip2:
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP