SPRUJC9B March   2025  – January 2026 AM62L

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
      1. 1.1.1 AM62Lx Processor Family Peripherals and IOs Change Summary (With Respect to AM62x Processor Family)
    2. 1.2 Processor-Specific SDK
    3. 1.3 Peripheral Circuit Implementation - Compatibility Between Processor Families
      1. 1.3.1 AM62Lx Processor Family Specific Implementation
      2. 1.3.2 Implementation Reference
    4. 1.4 Selection of Required Processor OPN (Orderable Part Number)
      1. 1.4.1 Processor Support for Secure Boot and Functional Safety
    5. 1.5 Technical Documentation
      1. 1.5.1 Updated EVM Schematic With Design, Review and Cad Notes Added
      2. 1.5.2 Collaterals on TI.com, Processor Product Page
      3. 1.5.3 Schematic Design Guidelines and Schematic Review Checklist - Processor Family Specific User's Guide
      4. 1.5.4 Updates to Hardware Design Considerations User's Guide
      5. 1.5.5 Processor and Peripherals Related FAQs to Support Custom Board Designs
    6. 1.6 Custom Board Design Documentation
    7. 1.7 Processor and Processor Peripherals Design Related Queries During Custom Board Design
  5. 2 Custom Board Design Block Diagram
    1. 2.1 Developing the Custom Board Design Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Configuring the Processor Pins Functionality (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Processor Supply (Power) Rails (Operating Voltage)
      1. 3.2.1 Supported Low-Power Modes
      2. 3.2.2 Processor Core and Peripheral Core - Power Supply
      3. 3.2.3 Peripherals Power Supply
      4. 3.2.4 Processor IO Supply for IO Group Power Supply
        1. 3.2.4.1 1.8V or 3.3V Dual-Voltage IO Supply for IO Group Power Supply
          1. 3.2.4.1.1 Additional Information
        2. 3.2.4.2 1.8V Fixed IO Supply for IO Group Power Supply
      5. 3.2.5 Integrated LDO for SD Card Interface IO Supply Switching (Dynamic Switching Dual-voltage IO Supply for MMC1 IO)
      6. 3.2.6 VPP (eFuse ROM Programming) Power Supply
      7. 3.2.7 Internal LDOs for Dual-voltage IO Supply for IO Groups (Processor)
    3. 3.3 Power Supply Filtering
    4. 3.4 Power Supply Decoupling and Bulk Capacitors
      1. 3.4.1 Note on PDN Target Impedance
    5. 3.5 Power Supply Sequencing
    6. 3.6 Power Supply Diagnostics (Voltage Monitor Pins VMON)
    7. 3.7 Power Supply Diagnostics (Monitoring Using External Monitoring Circuit (Devices))
    8. 3.8 Custom Board Current Requirements Estimation and Supply Sizing
  7. 4 Processor Clock (Input and Output)
    1. 4.1 Processor Clocking (External Crystal or External Oscillator)
      1. 4.1.1 LFOSC0 Connection When Unused
      2. 4.1.2 WKUP_OSC0 and LFOSC0, Crystal Selection
      3. 4.1.3 LVCMOS Compatible Digital Clock Input Source
    2. 4.2 Processor Clock Outputs
      1. 4.2.1 Observation Clock Outputs
    3. 4.3 Clock Tree Tool
  8. 5 Joint Test Action Group (JTAG)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 BSDL File
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection Recommendations for JTAG Interface Signals
      4. 5.1.4 Debug Boot Modes and Boundary Scan Compliance
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
      1. 6.1.1 RTC Power-on Reset (RTC_PORz)
    2. 6.2 Latching of Processor Boot Mode Configuration Inputs
    3. 6.3 Resetting of the Attached Devices
    4. 6.4 Watchdog Timer
  10. 7 Processor - Peripherals Connection
    1. 7.1  Supported Processor Cores
    2. 7.2  Selecting Peripherals Across Domains
    3. 7.3  Memory Controller (DDRSS)
      1. 7.3.1 Processor DDR Subsystem and Device Registers Configuration
      2. 7.3.2 DDR0_CAL0 (IO Pad Calibration Resistor) Connection for DDRSS
      3. 7.3.3 Attached Memory Device ZQ and Reset_N (Memory Device Reset) Connection
      4. 7.3.4 Unused Signals (Pins) on the Memory Device
    4. 7.4  Media, Data Storage Interfaces (MMC0, MMC1, MMC2, OSPI0/QSPI0 and GPMC0)
      1. 7.4.1 Multi-Media Card/Secure Digital (MMCSD) Interface (MMC0, MMC1, MMC2)
      2. 7.4.2 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
      3. 7.4.3 General-Purpose Memory Controller (GPMC0) Interface
    5. 7.5  Ethernet Interface
      1. 7.5.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
    6. 7.6  Programmable Real-Time Unit Subsystem (PRUSS)
    7. 7.7  Universal Serial Bus (USB) Subsystem
    8. 7.8  General Connectivity Peripherals
      1. 7.8.1 Inter-Integrated Circuit (I2C) Interface
    9. 7.9  Analog-to-Digital Converter (ADC0)
    10. 7.10 Display Subsystem (DSS)
    11. 7.11 Connection of Processor Power Supply Pins, IOs and Peripherals When not Used
      1. 7.11.1 External Interrupt (EXTINTn)
      2. 7.11.2 External Wakeup Inputs (EXT_WAKEUP0 and EXT_WAKEUP1)
      3. 7.11.3 RSVD0 Reserved Pin (Signal)
    12. 7.12 EVM Specific Circuit Implementation (Reuse)
  11. 8 Interfacing of Processor IOs (LVCMOS or SDIO or Open-Drain, Fail-Safe Type IO Buffers) and Performing Simulations
    1. 8.1 IBIS Model
    2. 8.2 IBIS-AMI Model
  12. 9 Processor Current Draw and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current Rating for Different Supply Rails
    3. 9.3 Supported Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 Thermal Model
      2. 9.4.2 Voltage Thermal Management Module (VTM)
  13. 10Schematic:- Capture, Entry and Review
    1. 10.1 Custom Board Design Passive Components and Values Selection
    2. 10.2 Custom Board Design Electronic Computer Aided Design (ECAD) Tools Considerations
    3. 10.3 Custom Board Design Schematic Capture
    4. 10.4 Custom Board Design Schematic Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 DDR Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signals Routing Guidelines
    4. 11.4 Processor-Specific EVM Board Layout
    5. 11.5 Custom Board Layer Count and Layer Stack-up
      1. 11.5.1 Simulation Recommendations
    6. 11.6 DDR-MARGIN-FW
    7. 11.7 Reference for Steps to be Followed for Running Board Simulation
    8. 11.8 Software Development Training (Academy) for Processors
  15. 12Custom Board Assembly and Testing
    1. 12.1 Custom Board Bring-up Tips and Debug Guidelines
  16. 13Processor (Device) Handling and Assembly
    1. 13.1 Processor (Device) Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14Terminology
  18. 15References
    1. 15.1 Processor-Specific (AM62Lx)
    2. 15.2 Common
  19. 16Revision History

14 Terminology

    ADC Analog-to-Digital Converter
    BSDL Boundary-Scan Description Language
    CAN-FD Controller Area Network Flexible Data-Rate
    CPPI Communications Port Programming Interface
    CPSW3G Common Platform Ethernet Switch 3-port Gigabit
    DPI Display Parallel Interface
    DSI Display Serial Interface
    DSITX Display Serial Interface Transmitter
    DRD Dual-Role Device
    E2E Engineer to Engineer
    ECAD Electronic Computer Aided Design
    ECAP Enhanced Capture
    ECC Error-Correcting Code
    eMMC embedded Multi-Media Card
    EMU Emulation Control
    EPWM Enhanced Pulse-Width Modulator
    EQEP Enhanced Quadrature Encoder Pulse
    FAQ Frequently Asked Question
    GPIO General Purpose Input/Output
    GPMC General-Purpose Memory Controller
    HS-RTDX High-Speed Real Time Data eXchange
    I2C Inter-Integrated Circuit
    IBIS Input/Output Buffer Information Specification
    JTAG Joint Test Action Group
    LDO Low-Dropout
    LVCMOS Low Voltage Complementary Metal Oxide Semiconductor
    MAC Media Access Controller
    MCAN Modular Controller Area Network
    MCASP Multichannel Audio Serial Ports
    MCSPI Multichannel Serial Peripheral Interfaces
    MCU Micro Controller Unit
    MMC Multi-Media Card
    MSL Moisture Sensitivity Level
    OSPI Octal Serial Peripheral Interface
    OTP One-Time Programmable
    PCB Printed Circuit Board
    PDN Power Distribution Network
    PMIC Power Management Integrated Circuit
    POR Power-on Reset
    QSPI Quad Serial Peripheral Interface
    RGMII Reduced Gigabit Media Independent Interface
    RMII Reduced Media Independent Interface
    ROC Recommended Operating Condition
    RTC Real-Time Clock
    SD Secure Digital
    SDIO Secure Digital Input Output
    SDK Software Development Kit
    SPI Serial Peripheral Interface
    TCK Test Clock Input
    TDI Test Data Input
    TDO Test Data Output
    TMS Test Mode Select Input
    TRM Technical Reference Manual
    TRSTn Test Reset
    UART Universal Asynchronous Receiver/Transmitter
    USB Universal Serial Bus
    VCA Via Channel Array
    VTM Voltage Thermal Management Module
    WKUP Wakeup
    XDS eXtended Development System