SPRUJC9B March   2025  – January 2026 AM62L

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
      1. 1.1.1 AM62Lx Processor Family Peripherals and IOs Change Summary (With Respect to AM62x Processor Family)
    2. 1.2 Processor-Specific SDK
    3. 1.3 Peripheral Circuit Implementation - Compatibility Between Processor Families
      1. 1.3.1 AM62Lx Processor Family Specific Implementation
      2. 1.3.2 Implementation Reference
    4. 1.4 Selection of Required Processor OPN (Orderable Part Number)
      1. 1.4.1 Processor Support for Secure Boot and Functional Safety
    5. 1.5 Technical Documentation
      1. 1.5.1 Updated EVM Schematic With Design, Review and Cad Notes Added
      2. 1.5.2 Collaterals on TI.com, Processor Product Page
      3. 1.5.3 Schematic Design Guidelines and Schematic Review Checklist - Processor Family Specific User's Guide
      4. 1.5.4 Updates to Hardware Design Considerations User's Guide
      5. 1.5.5 Processor and Peripherals Related FAQs to Support Custom Board Designs
    6. 1.6 Custom Board Design Documentation
    7. 1.7 Processor and Processor Peripherals Design Related Queries During Custom Board Design
  5. 2 Custom Board Design Block Diagram
    1. 2.1 Developing the Custom Board Design Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Configuring the Processor Pins Functionality (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Processor Supply (Power) Rails (Operating Voltage)
      1. 3.2.1 Supported Low-Power Modes
      2. 3.2.2 Processor Core and Peripheral Core - Power Supply
      3. 3.2.3 Peripherals Power Supply
      4. 3.2.4 Processor IO Supply for IO Group Power Supply
        1. 3.2.4.1 1.8V or 3.3V Dual-Voltage IO Supply for IO Group Power Supply
          1. 3.2.4.1.1 Additional Information
        2. 3.2.4.2 1.8V Fixed IO Supply for IO Group Power Supply
      5. 3.2.5 Integrated LDO for SD Card Interface IO Supply Switching (Dynamic Switching Dual-voltage IO Supply for MMC1 IO)
      6. 3.2.6 VPP (eFuse ROM Programming) Power Supply
      7. 3.2.7 Internal LDOs for Dual-voltage IO Supply for IO Groups (Processor)
    3. 3.3 Power Supply Filtering
    4. 3.4 Power Supply Decoupling and Bulk Capacitors
      1. 3.4.1 Note on PDN Target Impedance
    5. 3.5 Power Supply Sequencing
    6. 3.6 Power Supply Diagnostics (Voltage Monitor Pins VMON)
    7. 3.7 Power Supply Diagnostics (Monitoring Using External Monitoring Circuit (Devices))
    8. 3.8 Custom Board Current Requirements Estimation and Supply Sizing
  7. 4 Processor Clock (Input and Output)
    1. 4.1 Processor Clocking (External Crystal or External Oscillator)
      1. 4.1.1 LFOSC0 Connection When Unused
      2. 4.1.2 WKUP_OSC0 and LFOSC0, Crystal Selection
      3. 4.1.3 LVCMOS Compatible Digital Clock Input Source
    2. 4.2 Processor Clock Outputs
      1. 4.2.1 Observation Clock Outputs
    3. 4.3 Clock Tree Tool
  8. 5 Joint Test Action Group (JTAG)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 BSDL File
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection Recommendations for JTAG Interface Signals
      4. 5.1.4 Debug Boot Modes and Boundary Scan Compliance
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
      1. 6.1.1 RTC Power-on Reset (RTC_PORz)
    2. 6.2 Latching of Processor Boot Mode Configuration Inputs
    3. 6.3 Resetting of the Attached Devices
    4. 6.4 Watchdog Timer
  10. 7 Processor - Peripherals Connection
    1. 7.1  Supported Processor Cores
    2. 7.2  Selecting Peripherals Across Domains
    3. 7.3  Memory Controller (DDRSS)
      1. 7.3.1 Processor DDR Subsystem and Device Registers Configuration
      2. 7.3.2 DDR0_CAL0 (IO Pad Calibration Resistor) Connection for DDRSS
      3. 7.3.3 Attached Memory Device ZQ and Reset_N (Memory Device Reset) Connection
      4. 7.3.4 Unused Signals (Pins) on the Memory Device
    4. 7.4  Media, Data Storage Interfaces (MMC0, MMC1, MMC2, OSPI0/QSPI0 and GPMC0)
      1. 7.4.1 Multi-Media Card/Secure Digital (MMCSD) Interface (MMC0, MMC1, MMC2)
      2. 7.4.2 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
      3. 7.4.3 General-Purpose Memory Controller (GPMC0) Interface
    5. 7.5  Ethernet Interface
      1. 7.5.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
    6. 7.6  Programmable Real-Time Unit Subsystem (PRUSS)
    7. 7.7  Universal Serial Bus (USB) Subsystem
    8. 7.8  General Connectivity Peripherals
      1. 7.8.1 Inter-Integrated Circuit (I2C) Interface
    9. 7.9  Analog-to-Digital Converter (ADC0)
    10. 7.10 Display Subsystem (DSS)
    11. 7.11 Connection of Processor Power Supply Pins, IOs and Peripherals When not Used
      1. 7.11.1 External Interrupt (EXTINTn)
      2. 7.11.2 External Wakeup Inputs (EXT_WAKEUP0 and EXT_WAKEUP1)
      3. 7.11.3 RSVD0 Reserved Pin (Signal)
    12. 7.12 EVM Specific Circuit Implementation (Reuse)
  11. 8 Interfacing of Processor IOs (LVCMOS or SDIO or Open-Drain, Fail-Safe Type IO Buffers) and Performing Simulations
    1. 8.1 IBIS Model
    2. 8.2 IBIS-AMI Model
  12. 9 Processor Current Draw and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current Rating for Different Supply Rails
    3. 9.3 Supported Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 Thermal Model
      2. 9.4.2 Voltage Thermal Management Module (VTM)
  13. 10Schematic:- Capture, Entry and Review
    1. 10.1 Custom Board Design Passive Components and Values Selection
    2. 10.2 Custom Board Design Electronic Computer Aided Design (ECAD) Tools Considerations
    3. 10.3 Custom Board Design Schematic Capture
    4. 10.4 Custom Board Design Schematic Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 DDR Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signals Routing Guidelines
    4. 11.4 Processor-Specific EVM Board Layout
    5. 11.5 Custom Board Layer Count and Layer Stack-up
      1. 11.5.1 Simulation Recommendations
    6. 11.6 DDR-MARGIN-FW
    7. 11.7 Reference for Steps to be Followed for Running Board Simulation
    8. 11.8 Software Development Training (Academy) for Processors
  15. 12Custom Board Assembly and Testing
    1. 12.1 Custom Board Bring-up Tips and Debug Guidelines
  16. 13Processor (Device) Handling and Assembly
    1. 13.1 Processor (Device) Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14Terminology
  18. 15References
    1. 15.1 Processor-Specific (AM62Lx)
    2. 15.2 Common
  19. 16Revision History

2.2 Configuring the Boot Mode

The processor family supports reduced pin count (x4 pins) or full pin count (x16 pins) boot modes. The processor family additionally supports eFuse BOOTMODE1 and eFuse BOOTMODE2. Custom board designers have the flexibility to choose the required boot mode to optimize use of external resistors.

For supported boot mode configurations, see the following FAQ:

[FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62Ax / AM62Px / AM62D-Q1 / AM62L - Supported bootmode configurations

The recommendation is to indicate the configured boot mode and the boot mode provisions provided in the block diagram. The recommendation is to include the primary boot and backup boot configurations (reduced pin count or full pin count or eFuse).

The processor family supports multiple peripheral interfaces that can be configured for boot. For the available boot mode configurations and supported peripherals, see the device-specific TRM. The processor family supports primary boot mode and an optional backup boot mode configuration. If the primary boot (source) mode fails, the ROM switches to the backup boot mode.

The processor family supports x2 (two) BOOTMODE pin mapping options:

  1. Reduced Pin count - Using only 4 of the 16 bootstrap pins BOOTMODE [15:12]
  2. Full Pin count - Using all 16 of the bootstrap pins BOOTMODE [15:0]

The reduced pin count option is implemented in hardware, and is transparent to the ROM code. Its implementation is a look-up table that uses four pins to select from either the full pin count option, or a set of commonly used boot modes selected as reduced pin count options. The selection determines what value is loaded into the Device Status Register WKUP_CTRL_MMR_CFG1_DEVSTAT[15:0] on a POR. The boot mode configuration inputs are recommended to be stable before releasing (deassertion) the PORz input.

The reduced pin count boot mode configuration offers the advantage of requiring less boot mode configuration pins and external resistors, which can translate to use of fewer resistors (pullup or pulldown). The reduced pin count boot mode supports fewer pin selectable boot mode options.

However, two (eFuse BOOTMODE1, eFuse BOOTMODE2) of the reduced pin count configuration options selectable from the Reduced BOOTMODE Pin Mapping table can be configured to support any of the full 16-bit boot options by programming the required boot mode configuration into the eFuse. To program the eFuse, a dedicated supply generated using an LDO with provision to enable only while writing to the eFuse is required to be connected to the VPP pin.

Note: The recommendation is to provide provision to connect the VPP supply (Using on-board LDO or connect an external supply for production programming using a test point provided for the processor VPP pin along with on-board capacitors added and a processor IO used to control the VPP supply timing) to the processor VPP pin used for eFuse programming. For more information, see the Section 3.2.6.

To reduce the number of pullup/pulldown resistors used for configuring the boot modes, the input buffers for BOOTMODE [11:0] pins are disabled during POR unless BOOTMODE [15:14] are set to '00'. Disabling the buffers avoids power consumption due to floating inputs on these pins when the reduced pin count boot mode configuration is used. For more information, see the device-specific TRM.

Reduced Pin Count Boot Mode:

Reduced pin count boot mode uses BOOTMODE [15:12] (x4 pins) and the configuration is summarized below:

BOOTMODE [13:12] – The boot mode pins are used to configure the required primary and secondary boot mode or eFuse BOOTMODE1/eFuse BOOTMODE2

BOOTMODE [15:14] – The boot mode pins are used to select the boot mode configuration (reduced or full pin count). For more information, see the device-specific TRM.

Note: BOOTMODE [11:00] – IO buffers are off during reset and after reset. The boot mode input (IOs) pins can be left unconnected when the IOs are not configured for alternate function. When the IOs are configured for alternate functions, the recommendation is to connect the boot mode input (IOs) pins to the alternate function through a 0Ω series resistors. The series resistors can be used to isolate the alternate function during testing.
Note: Leaving BOOTMODE [15:12] pins unconnected is not recommended or allowed option.

Full Pin Count Boot Mode:

Full pin count boot mode uses BOOTMODE [15:00] (x16 pins) and the configuration is summarized below:

PLL Config (Configuration): BOOTMODE [02:00] – PLL config pins are used to indicate the system clock (PLL reference clock selection) frequency (WKUP_OSC0_XI/XO) to ROM code for PLL configuration

Note: For supported crystal frequency see the processor-specific data sheet. Configure the boot mode to match the supported crystal or clock frequency. Wrong clock frequency configuration affects the processor performance including resetting of the board.

Primary Boot Mode: BOOTMODE [06:03] – The boot mode pins are used to configure the required primary boot mode, the peripheral/memory to boot from

Primary Boot Mode Config: BOOTMODE [09:07] – The boot mode configuration pins support optional configurations for primary boot and are used in conjunction with the primary boot mode selection pins

Backup Boot Mode: BOOTMODE [12:10] – The boot mode pins are used to configure the required backup boot mode, the peripheral/memory to boot from, in case primary boot fails

Backup Boot Mode Config: BOOTMODE [13] – The boot mode pin provides additional configuration options (optional - depends on the selected backup boot mode pins)

BOOTMODE [15:14] – The boot mode pins are used to select the boot mode configuration (reduced or full pin count). For configuration, see the device-specific TRM

Note: Leaving BOOTMODE [15:00] pins unconnected is not recommended or allowed option.

For more information on full and reduced pin count boot mode mappings, see the Boot Mode Pin Mapping Options section of device-specific TRM.

Key considerations when configuring boot mode:

  • The recommendation is to always include provision to configure boot modes used during the custom board development phase, such as USB boot (USB0, DFU), UART boot (UART0) or no-boot/Dev boot mode for debug (using JTAG)
  • Boot mode input pins support alternate functions that can be configured after the boot mode configuration inputs have been latched. The recommendation is to take into consideration the alternate function implemented when choosing pullup or pulldown resistors during custom board design. In case the boot mode inputs are being driven by external inputs to support test automation or remote configuration, the boot mode inputs are required to return to the required boot configuration value (level) whenever the processor is reset (indicated by RESETSTATz, reset status output pin) to allow the processor to boot correctly.

For information related to supported boot modes, see the Initialization chapter of the device-specific TRM and device-specific silicon errata.

For implementing the required boot mode (reduced pin count or full pin count), see the EVM TMDS62LEVM schematic.

Note: Custom board designers are responsible for providing provision to set the required boot mode configuration (using pullups or pulldowns, or optionally using jumpers/switches (with provision for external ESD protection when set in uncontrolled ESD environment)). The recommendation is to provide provision for pullup and pulldown for the boot mode input pins that have configuration capability for increase design flexibility. Shorting of multiple boot mode input pins together, leaving any of the boot mode input pins unconnected or connecting the boot mode inputs directly to supply or ground is not recommended or allowed.
Note:

When full pin count boot mode option is configured, each of these boot mode input pins (BOOTMODE [15:0]) are recommended to be connected to the corresponding power supply or VSS through separate external pull resistor to make sure the boot mode input pins are held to a valid logic high or low level as appropriate to select the desired device boot mode.

When reduced pin count boot mode option is configured, each of these boot mode input pins (BOOTMODE [15:12]) are required to be connected to the corresponding power supply or VSS through separate external pull resistor to make sure the boot mode input pins are held to a valid logic high or low level as appropriate to select the desired device boot mode.

Note: The recommendation is to connect the processor boot mode input pins (configured for alternate function) to the alternate function through a 0Ω series resistor. Series resistor can be used to isolate the alternate function during testing.
Note: Boot mode configuration resistors are recommended to be pulled to VDDSHV0.
Note: When boot mode configuration is set using eFuse, provision to connect the VPP supply is recommended.
Note: For reduced pin count boot mode configuration, 25MHz (Crystal or LVCMOS digital clock) is the only supported clock frequency.

For full pin count boot mode, see the device-specific data sheet for the supported clock frequencies and the device-specific TRM to configure the supported clock frequency.

For implementing the boot mode, see the following FAQs:

[FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62A / AM62P / AM62D-Q1 / AM62L - Bootmode implementation with isolation buffers used

[FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62A / AM62P / AM62D-Q1 / AM62L - Bootmode implementation without isolation buffers