SPRZ425G November   2014  – November 2026 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     i202
    2.     i694
    3.     i709
    4.     i727
    5.     i729
    6.     i767
    7.     i813
    8.     i814
    9.     i826
    10.     i829
    11.     i866
    12.     i868
    13.     i872
    14.     i874
    15.     i879
    16.     i882
    17.     i883
    18.     i888
    19.     i889
    20.     i891
    21.     i893
    22.     i894
    23.     i898
    24.     i899
    25.     i904
    26.     i911
    27.     i914
    28.     i915
    29.     i916
    30.     i924
    31.     i930
    32.     i936
    33.     i938
    34.     i939
    35.     i940
  4. 3Silicon Limitations
    1.     i833
    2.     i873
    3.     i876
    4.     i877
    5.     i892
  5. 4Silicon Cautions
    1.     i781
    2.     i827
    3.     i828
    4.     i836
    5.     i839
    6.     i864
    7.     i886
    8.     i908
    9.     i912
    10.     i923
  6. 5Revision History

i936

DSS LCD/DPI Out Field Reversal in Interlaced RGB Mode

CRITICALITY

High

DESCRIPTION

Interlaced RGB mode if set on DSS DPI outputs (VOUT1/2/3) can result in display artifacts due to field reversal. DSS does not support an interlaced compliant VSYNC signal on the DPI output. If the external device/monitor hooked to the DSS in this mode requires an interlaced compliant VSYNC signal then it will have this issue randomly. If the external monitor is able to lock the polarity correctly then the display will be correct otherwise the display will generate field reversed view.

WORKAROUND

Use Interlaced YUV mode with embedded sync (BT.656, BT.1120) if possible.

REVISIONS IMPACTED

SR 2.0A, 2.0, 1.0A, 1.0

TDA3x: 2.0A, 2.0, 1.0A, 1.0

DRA78x: 2.0A, 2.0

DM50x: 2.0