SPRZ425G November   2014  – November 2026 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     i202
    2.     i694
    3.     i709
    4.     i727
    5.     i729
    6.     i767
    7.     i813
    8.     i814
    9.     i826
    10.     i829
    11.     i866
    12.     i868
    13.     i872
    14.     i874
    15.     i879
    16.     i882
    17.     i883
    18.     i888
    19.     i889
    20.     i891
    21.     i893
    22.     i894
    23.     i898
    24.     i899
    25.     i904
    26.     i911
    27.     i914
    28.     i915
    29.     i916
    30.     i924
    31.     i930
    32.     i936
    33.     i938
    34.     i939
    35.     i940
  4. 3Silicon Limitations
    1.     i833
    2.     i873
    3.     i876
    4.     i877
    5.     i892
  5. 4Silicon Cautions
    1.     i781
    2.     i827
    3.     i828
    4.     i836
    5.     i839
    6.     i864
    7.     i886
    8.     i908
    9.     i912
    10.     i923
  6. 5Revision History

i874

TIMER5/6/7/8 Interrupts Not Propagated

CRITICALITY

Low

DESCRIPTION

When TIMER5, TIMER6, TIMER7, or TIMER8 clocks are enabled (CM_IPU_TIMER5/6/7/8_CLKCTRL[1:0] MODULEMODE = 0x2:ENABLE) and the CD-IPU is in HW_AUTO mode (CM_IPU_CLKSTCTRL[1:0] CLKTRCTRL = 0x3:HW_AUTO) the corresponding TIMER will continue counting, but enabled interrupts will not be propagated to the destinations (MPU, DSP, etc) in the SoC until the TIMER registers are accessed from the CPUs (MPU, DSP etc.). This can result in missed timer interrupts.

WORKAROUND

In order for TIMER5/6/7/8 interrupts to be propagated and serviced correctly the CD_IPU domain should be set to SW_WKUP mode (CM_IPU_CLKSTCTRL[1:0] CLKTRCTRL = 0x2:SW_WKUP)

REVISIONS IMPACTED

SR 2.0A, 2.0, 1.0A, 1.0

TDA3x: 2.0A, 2.0, 1.0A, 1.0

DRA78x: 2.0A, 2.0

DM50x: 2.0