CRITICALITY

Medium

DESCRIPTION

Because of a glitchy structure inside the UART module, accessing the UART_MDR1 register may create a dummy underrun condition and freeze the UART in IrDa transmission. In UART mode, this may corrupt the transferred data(received or transmitted).

WORKAROUND

To ensure this problem does not occur, the following software initialization sequence must be used each time UART_MDR1 must be changed:

1. If needed, setup the UART by writing the required registers, except UART_MDR1
2. Set appropriately the UART_MDR1[2:0] MODE_SELECT bit field
3. Wait for 5 L4 clock cycles + 5 UART functional clock cycles
4. Clear TX and RX FIFO in UART_FCR register to reset its counter logic
5. Read UART_RESUME register to resume the halted operation

Step 5 is for IrDA mode only and can be omitted in UART mode.

REVISIONS IMPACTED

SR 2.0A, 2.0 , 1.0A, 1.0

TDA3x: 2.0A, 2.0, 1.0A, 1.0

DRA78x: 2.0A, 2.0

DM50x: 2.0