CRITICALITY

Medium

DESCRIPTION

The DSP1 and DSP2 Subsystems include MFlag output signals that are under DSP software control and are used to control arbitration at various points in the system interconnect and EMIF command queues. Each DSP subsystem's MFlag output signal is uninitialized in hardware until the DSP is powered up and clocked, and can default to a value of either 0 or 1. This can have unanticipated and non-deterministic effects on system traffic dependent on the power-on state of the MFlag signals.

WORKAROUND

In order to ensure that a known value is driven by the DSP's MFlag outputs, software should power-up the DSP(s) and enable the clocks for a brief time. After the DSP is enabled, it can immediately be disabled if desired. Once the DSP is enabled and clocked the MFlag output will be 0.

The sequence to perform a DSPn enable and then power down is as below:

	
    /* Start a SW force wakeup for DSPSS */
    WR_MEM_32(CM_DSPn_CLKSTCTRL, 0x2);
    
    /* Enable DSPSS clock */
    WR_MEM_32(CM_DSPn_DSPn_CLKCTRL, 0x1);
   
    /* Reset de-assertion for DSP SS logic */
    WR_MEM_32(RM_DSPn_RSTCTRL, 0x1);
    /* Wait till module is functional*/
    while ((RD_MEM_32(CM_DSPn_DSP_CLKCTRL) & 0x30000) != 0x0 or TIMEOUT(100ms));
    /* Make the DSPn CLK CTRL to HW auto */
    WR_MEM_32(CM_DSPn_CLKSTCTRL, 0x3);
    /* Make the DSPn POWER domain to go to power off mode */
    WR_MEM_32(PM_DSPn_PWRSTCTRL, (RD_MEM_32(PM_DSPn_PWRSTCTRL) & 0xFFFFFFF0));
    /* Disable DSPSS clock */
    WR_MEM_32(CM_DSPn_DSPn_CLKCTRL, 0x0);
    /* Reset assertion for DSP SS logic */
    WR_MEM_32(RM_DSPn_RSTCTRL, 0x3);
		

This sequence should be performed even for devices where one or both DSPs are not supported.

The timeout value shown in the while loop is recommended as a software best practice. The poll for completion should always succeed before the timeout expires.

REVISIONS IMPACTED

SR 2.0A, 2.0, 1.0A, 1.0

TDA3x: 2.0A, 2.0, 1.0A, 1.0

DRA78x: 2.0A, 2.0

DM50x: 2.0