SPRZ575A March   2024  – April 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2120
      5.      i2137
      6.      i2160
      7.      i2189
      8.      i2190
      9.      i2196
      10.      i2199
      11.      i2208
      12.      i2242
      13.      i2243
      14.      i2249
      15.      i2253
      16.      i2278
      17.      i2279
      18.      i2310
      19.      i2311
      20.      i2312
      21.      i2326
      22.      i2330
      23.      i2351
      24.      i2362
      25.      i2366
      26.      i2372
      27.      i2383
      28.      i2399
      29.      i2401
      30.      i2407
      31.      i2409
      32.      i2410
      33.      i2419
      34.      i2424
      35.      i2431
      36.      i2436
      37.      i2457
      38.      i2478
  5.   Trademarks
  6. 4Revision History

i2424

PLL: PLL Programming Sequence May Introduce PLL Instability

Details:

PLL programming sequence has been changed to ensure that, if used, all calibration fields are configured prior to enabling the PLL calibration. In addition to the change to the control of the calibration logic, other changes are implemented so that PLL parameters are unchanged while the PLL is enabled.

When in integer mode, the software enables the PLL calibration feature on calibration-capable PLLs. The previous software adjusted calibration modes after CAL_LOCK was asserted. These writes have been observed to cause a loss of PLL lock on some devices. Additionally, even on susceptible devices, the loss of lock is intermittent, but when it occurs, dependent circuitry runs at an incorrect frequency; this wrong frequency can show up as slow algorithm execution or communication failures.

Limit on the impact: The calibration logic cannot be used when the PLL is in fractional mode. Therefore, PLLs that are programmed to use fractional mode should not see a failure related to the calibration programmation. Nevertheless, because of the change to the full PLL sequence, the new software is recommended for all users.

Workaround(s):

Do not use clk_pll_16fft_cal_option4() in SYSFW. Ensure to use updated PLL programming sequences in SDK v10.0 or later when performing any PLL configuration change.