SPRZ575A March   2024  – April 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2120
      5.      i2137
      6.      i2160
      7.      i2189
      8.      i2190
      9.      i2196
      10.      i2199
      11.      i2208
      12.      i2242
      13.      i2243
      14.      i2249
      15.      i2253
      16.      i2278
      17.      i2279
      18.      i2310
      19.      i2311
      20.      i2312
      21.      i2326
      22.      i2330
      23.      i2351
      24.      i2362
      25.      i2366
      26.      i2372
      27.      i2383
      28.      i2399
      29.      i2401
      30.      i2407
      31.      i2409
      32.      i2410
      33.      i2419
      34.      i2424
      35.      i2431
      36.      i2436
      37.      i2457
      38.      i2478
  5.   Trademarks
  6. 4Revision History

i2401

CPSW: Host Timestamps Cause CPSW Port to Lock up

Details:

The CPSW offers two mechanisms for communicating packet ingress timestamp information to the host.

The first mechanism is via the CPTS Event FIFO which records timestamps when triggered by certain events. One such event is the reception of an Ethernet packet with a specified EtherType field. Most commonly this is used to capture ingress timestamps for PTP packets. With this mechanism the host must read the timestamp (from the CPTS FIFO) separately from the packet payload which is delivered via DMA. This mode is supported and is not affected by this errata.

The second mechanism is to enable receive timestamps for all packets, not just PTP packets. With this mechanism the timestamp is delivered alongside the packet payload via DMA. This second mechanism is the subject of this errata.

When the CPTS host timestamp is enabled, every packet to the internal CPSW port FIFO requires a timestamp from the CPTS. When the packet preamble is corrupted due to EMI or any other corruption mechanism a timestamp request may not be sent to the CPTS. In this case the CPTS will not produce the timestamp which causes a lockup condition in the CPSW port FIFO. When the CPTS host timestamp is disabled by clearing the tstamp_en bit in the CPTS_CONTROL register the lockup condition is prevented from occurring.

Workaround(s):

Ethernet to host timestamps must be disabled.

CPTS Event FIFO timestamping can be used instead of CPTS host timestamps.