1 Modules Affected

Table 1-1 shows the module(s) that are affected by each usage note.

Table 1-1 Usage Note by Modules

MODULE	USAGE NOTE
USB	i2134 — USB: 2.0 Compliance Receive Sensitivity Test Limitation

Table 1-2 shows the module(s) that are affected by each advisory.

Table 1-2 Advisories by Modules

MODULE	ADVISORY
BCDMA	i2431 — BCDMA: RX Channel can lockup in certain scenarios
	i2436 — BCDMA: BCDMA RX_IGNORE_LONG setting in RX CHAN CFG register doesn't work
Boot	i2366 — Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operation
	i2372 — Boot: ROM doesn't support select multi-plane addressing schemes in Serial NAND boot
	i2410 — Boot: ROM may fail to boot due to i2409
	i2419 — Boot: When disabling deskew calibration, ROM does not check if deskew calibration was enabled
	i2457 — Boot: Missing data in UART transfer causes boot failures
C7x SE	i2120 — C71x: SE Hangs on Non-Parity Error Detection in Transposed Streams With LEZR
	i2199 — C71x: SE returning incorrect data when non-aligned transposed stream crosses AM1 circular buffer boundary
	i2399 — C7x: CPU NLC Module Not Clearing State on Interrupt
CPSW	i2208 — CPSW: ALE IET Express Packet Drops
	i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock up
CSI	i2190 — CSI_RX_IF may enter unknown state following an incomplete frame
DDR	i2160 — DDR: Valid VRef Range Must be Defined During LPDDR4 Command Bus Training
	i2330 — DDRSS Register Configuration Tool Updates
DSS	i2097 — DSS: Disabling a Layer Connected to Overlay May Result in Synclost During the Next Frame
ECC AGGR	i2049 — ECC AGGR: Potential IP Clockstop/reset sequence hang due to pending ECC Aggregator interrupts
IA	i2196 — IA: Potential deadlock scenarios in IA
MCAN	i2278 — MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID
	i2279 — MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID
MMCSD	i2312 — MMCSD: HS200 and SDR104 Command Timeout Window Too Small
	i2478 — MMCSD0: HS400 Mode not supported
OSPI	i2189 — OSPI: Controller PHY Tuning Algorithm
	i2249 — OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable
	i2351 — OSPI: Controller does not support Continuous Read mode with NAND Flash
	i2383 — OSPI: 2-byte address is not supported in PHY DDR mode
PCIe	i2242 — PCIe: The SerDes PCIe Reference Clock Output is temporarily disabled while changing Data Rates
	i2243 — PCIe: Timing requirement for disabling output refclk during L1.2 substate is not met
	i2326 — PCIe: MAIN_PLLx operating in fractional mode, which is required for enabling SSC, is not compliant with PCIe Refclk jitter limits
PLL	i2424 — PLL: PLL Programming Sequence May Introduce PLL Instability
PRG	i2253 — PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failure
PSIL	i2137 — Clock stop operation can result in undefined behavior
RAT	i2062 — RAT: Error Interrupt Triggered Even When Error Logging Disable Is Set
Reset	i2407 — RESET: MCU_RESETSTATz unreliable when MCU_RESETz is asserted low
SGMII	i2362 — 10-100M SGMII: Marvell PHY does not ignore the preamble byte resulting in link failure
USART	i2310 — USART: Erroneous clear/trigger of timeout interrupt
	i2311 — USART: Spurious DMA Interrupts
USB	i2409 — USB2 PHY locks up due to short suspend