STDA041 October   2026 OPA690

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Design Summary
  5. 2Theory of Operation
    1. 2.1 Circuit Overview
    2. 2.2 Closed-loop Operation
    3. 2.3 FET Operation Region
  6. 3Design Procedure
    1. 3.1 Choosing FET
      1. 3.1.1 Ciss
      2. 3.1.2 Compliance Voltage Range
      3. 3.1.3 Safe Operating Area (SOA)
    2. 3.2 Rsense Selection
      1. 3.2.1 Effect of ESL
    3. 3.3 Opamp Selection
      1. 3.3.1 Bandwidth
      2. 3.3.2 Slew Rate
      3. 3.3.3 Opamp Output Current
  7. 4Design Based Component Selection
    1. 4.1 Design for Trise = 100ns
      1. 4.1.1 FET Selection
      2. 4.1.2 Rsense Selection
      3. 4.1.3 Opamp Selection
        1. 4.1.3.1 Bandwidth
        2. 4.1.3.2 Slew Rate
        3. 4.1.3.3 Output Current
    2. 4.2 Architecture Selection (Quick Reference)
  8. 5Circuit Architecture Selection
    1. 5.1 Single Feedback Method
    2. 5.2 Dual Feedback Method
    3. 5.3 Enhanced Dual Feedback Method
  9. 6Results
  10. 7Related Documentation

3.1.1 Ciss

In any practical gate drive circuit, parasitic inductance exists in the gate trace and bond-wire connections. The gate inductance, combined with the total effective capacitance at the gate node Ceff, including Ciss forms an LC tank circuit. An undamped LC rings at a natural resonant frequency when a fast step reaches the gate, causing oscillations in VGS and consequently in the output current, severely degrades transient response. A damping resistor Rdamp placed in series with the gate suppresses these oscillations by introducing sufficient resistance into the LC loop, critically damping the resonance and producing a clean, non-oscillatory gate-voltage transition.

The value of Rdamp must satisfy a key condition: Rdamp must be significantly larger than the output resistance Ro of both op amps and the FET's internal gate resistance Rg. Since both Ro and Rg are typically very small in high-speed designs,the combination becomes negligible compared with total series resistance at the gate node, making Rdamp the dominant resistance in the gate drive path. A practical value of 5Ω is selected for Rdamp satisfying the condition Rdamp>> Ro, and Rg, while keeping the gate-drive speed within the required range.

Since Rdamp is the dominant resistance at the gate node, the RC network forms a first-order low-pass filter with Ceff, and the bandwidth of this RC network is given by 1 / (2π × Rdamp × Ceff). This pole governs how fast the gate voltage can respond to a step input from the opamp, effectively setting the rise-time of the entire system. Therefore, to meet the required rise-time specification, the bandwidth of the RC filter must be greater than or equal to the response bandwidth. BW ≥ 0.35 / Trise, (Trise represents the desired rise-time). This condition directly constrains the maximum permissible value of Ceff and consequently Ciss of the selected FET.

Assuming a first-order system, the required bandwidth relates to the rise-time according to Equation 2.

Equation 2. B W   ≥   0.35 T r i s e

The bandwidth of the RC gate network is given by Equation 3

Equation 3. B W   =   1 2 π ×   R d a m p ×   C e f f

Equating these two expressions gives the fundamental Ciss constraint:

Equation 4. C e f f ≤   T r i s e ( 2 π ×   R d a m p ×   0.35 )

This inequality defines the maximum allowable total effective gate capacitance that the selected FET must satisfy to meet the rise-time specification.