TIDUD61E October   2020  – April 2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Input AC Voltage Sensing
      2. 2.2.2 Bus Voltage Sensing
      3. 2.2.3 AC Current Sensing
      4. 2.2.4 Sense Filter
      5. 2.2.5 Protection (CMPSS)
    3. 2.3 Highlighted Products
      1. 2.3.1 C2000™ MCU F28004x
      2. 2.3.2 LMG3410R070
      3. 2.3.3 UCC27714
    4. 2.4 System Design Theory
      1. 2.4.1 PWM
      2. 2.4.2 Current Loop Model (PFC and Inverter mode)
      3. 2.4.3 DC Bus Regulation Loop (for PFC mode only)
      4. 2.4.4 Soft Start Around Zero Crossing for Eliminate or Reduce Current Spike
      5. 2.4.5 AC Drop Test
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Base Board Settings
        2. 3.1.1.2 Control Card Settings
      2. 3.1.2 Software
        1. 3.1.2.1 Opening Project Inside CCS
        2. 3.1.2.2 Project Structure
        3. 3.1.2.3 Using CLA on C2000 MCU to Alleviate CPU Burden
        4. 3.1.2.4 CPU and CLA Utilization and Memory Allocation
        5. 3.1.2.5 Running the Project
          1. 3.1.2.5.1 Lab 1: Open Loop, DC (PFC Mode)
            1. 3.1.2.5.1.1 Setting Software Options for LAB 1
            2. 3.1.2.5.1.2 Building and Loading Project
            3. 3.1.2.5.1.3 Setup Debug Environment Windows
            4. 3.1.2.5.1.4 Using Real-Time Emulation
            5. 3.1.2.5.1.5 Running Code
          2. 3.1.2.5.2 Lab 2: Closed Current Loop DC (PFC)
            1. 3.1.2.5.2.1 Setting Software Options for Lab 2
            2. 3.1.2.5.2.2 Designing Current Loop Compensator
            3. 3.1.2.5.2.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.2.4 Running Code
          3. 3.1.2.5.3 Lab 3: Closed Current Loop, AC (PFC)
            1. 3.1.2.5.3.1 Setting Software Options for Lab 3
            2. 3.1.2.5.3.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.3.3 Running Code
          4. 3.1.2.5.4 Lab 4: Closed Voltage and Current Loop (PFC)
            1. 3.1.2.5.4.1 Setting Software Options for Lab 4
            2. 3.1.2.5.4.2 Designing Voltage Loop Compensator
            3. 3.1.2.5.4.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.4.4 Running Code
          5. 3.1.2.5.5 Lab 5: Open loop, DC (Inverter)
            1. 3.1.2.5.5.1 Setting Software Options for Lab 5
            2. 3.1.2.5.5.2 Building and Loading Project
            3. 3.1.2.5.5.3 Setup Debug Environment Windows
            4. 3.1.2.5.5.4 Running Code
          6. 3.1.2.5.6 Lab 6: Open loop, AC (Inverter)
            1. 3.1.2.5.6.1 Setting Software Options for Lab 6
            2. 3.1.2.5.6.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.6.3 Running Code
          7. 3.1.2.5.7 Lab 7: Closed Current Loop, DC (Inverter with resistive load)
            1. 3.1.2.5.7.1 Setting Software Options for Lab 7
            2. 3.1.2.5.7.2 Designing Current Loop Compensator
            3. 3.1.2.5.7.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.7.4 Running Code
          8. 3.1.2.5.8 Lab 8: Closed Current Loop, AC (Inverter with resistive load)
            1. 3.1.2.5.8.1 Setting Software Options for Lab 8
            2. 3.1.2.5.8.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.8.3 Running Code
          9. 3.1.2.5.9 Lab 9: Closed Current Loop (Grid Connected Inverter)
            1. 3.1.2.5.9.1 Setting Software Options for Lab 9
            2. 3.1.2.5.9.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.9.3 Running Code: Emulated Grid-tied Condition (Verification purpose only)
            4. 3.1.2.5.9.4 Running Code: Grid-tied Condition
        6. 3.1.2.6 Running Code on CLA
        7. 3.1.2.7 Advanced Options
          1. 3.1.2.7.1 Input Cap Compensation for PF Improvement Under Light Load
          2. 3.1.2.7.2 83
          3. 3.1.2.7.3 Adaptive Dead Time for Efficiency Improvements
          4. 3.1.2.7.4 Phase Shedding for Efficiency Improvements
          5. 3.1.2.7.5 Non-Linear Voltage Loop for Transient Reduction
          6. 3.1.2.7.6 Software Phase Locked Loop Methods: SOGI - FLL
    2. 3.2 Testing and Results
      1. 3.2.1 Test Results at Input 120 Vrms, 60 Hz, Output 380-V DC
        1. 3.2.1.1 Startup
        2. 3.2.1.2 Steady State Condition
        3. 3.2.1.3 Transient Test With Step Load Change
          1. 3.2.1.3.1 0% to 50% Load Step Change
          2. 3.2.1.3.2 50% to 100% Load Step Change
          3. 3.2.1.3.3 100% to 50% Load Step Change
          4. 3.2.1.3.4 50% to 100% Load Step Change
      2. 3.2.2 Test Results at Input 230 Vrms, 50 Hz, Output 380 V DC
        1. 3.2.2.1 Startup
        2. 3.2.2.2 Steady State Condition
        3. 3.2.2.3 Transient Test With Step Load Change
          1. 3.2.2.3.1 33% to 100% Load Step Change
          2. 3.2.2.3.2 100% to 33% Load Step Change
      3. 3.2.3 Test Results Graphs
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7About the Author
  13. 8Revision History

2.4.2 Current Loop Model (PFC and Inverter mode)

The same control loop model applies to both PFC and grid-tied inverter operation. To understand the current loop model, first look at the inductor current closely. In Figure 2-8 the Duty cycle (D) is provided to the PWM modulator, which is connected to the switch Q3 and Q4. From here, Equation 1 is written as:

Equation 1. GUID-085FB6AC-E260-40CF-A488-390A1BC7E6BB-low.gif
Note:

When D is set to 1, Q3 is on all the time, and when D is 0, Q3 is off all the time.

To modulate the current through the inductor, the voltage GUID-6A6C9E82-9CC8-4ABE-9278-EDB05AE3EB9B-low.gifis regulated using the duty cycle control of Q3 and Q4 switches. It is assumed that the direction of current is positive in the direction from the AC line into the rectifier and that the grid is fairly stiff when using the DC bus feedforward and the AC voltage feedforward. Figure 2-9 shows the simplified current loop, and the current loop plant model is written as Equation 2.

Equation 2. GUID-49A6D866-D21E-4020-AFF4-A7643DA80992-low.gif

Where:

  • Kv_gain is the inverse of maximum bus voltage sensed,
  • Kvac_gain is the inverse of maximum AC voltage sensed, (A factor to normalize this is applied in the feedforward and hence the current loop model is only dependent on the Kv_gain)
  • GUID-98F4CF39-AAF1-4118-A00D-02E9B0429F6A-low.gif is the inverse of maximum AC current sensed, GUID-C11D8303-B7D2-4D8E-B27A-BC74F7695695-low.gif
  • GUID-26CB09E6-5FC7-49DF-A5D0-B9F4ABAD333C-low.gif is the response of the RC filter connected from the current sensor to the ADC pin
  • GUID-05444DCC-8810-4615-8D33-7284AE8C594B-low.gif is the digital delay associated with the PWM update and digital control is the current command
  • GUID-8357DFCA-13D4-4B9A-83E7-AA5B5E6DB32F-low.gif is the current command
GUID-C42AE45C-D5C5-4143-9EB3-68EC359AD01D-low.gifFigure 2-9 Current Loop Control Model
Note:

The negative sign on the reference is because the current loop is thought to be regulating the voltage, GUID-6A6C9E82-9CC8-4ABE-9278-EDB05AE3EB9B-low.gif. To increase the current, GUID-6A6C9E82-9CC8-4ABE-9278-EDB05AE3EB9B-low.gif must be reduced—hence, the opposite sign for reference and feedback in Figure 2-9.

This current loop model is then used to design the current compensator. A simple proportional integral controller is used for the current loop.

Now, in the case of three interleaved phases, the current is simply three times more as the same duty cycle is provided to each leg. Hence, the plant model is given as Equation 3.

Equation 3. GUID-B95C3B4F-7E39-4D6D-BA4F-E3D5E16D4916-low.gif

This model is verified on this design using the SFRA library. Figure 2-10 shows the model versus measured open loop frequency response, which shows good correlation between the two.

GUID-C935C54D-6B6E-4422-8F38-761095DD6585-low.gifFigure 2-10 Gi, Current Open Loop Gain Measured Verus Modelled