TIDUD61E October   2020  – April 2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Input AC Voltage Sensing
      2. 2.2.2 Bus Voltage Sensing
      3. 2.2.3 AC Current Sensing
      4. 2.2.4 Sense Filter
      5. 2.2.5 Protection (CMPSS)
    3. 2.3 Highlighted Products
      1. 2.3.1 C2000™ MCU F28004x
      2. 2.3.2 LMG3410R070
      3. 2.3.3 UCC27714
    4. 2.4 System Design Theory
      1. 2.4.1 PWM
      2. 2.4.2 Current Loop Model (PFC and Inverter mode)
      3. 2.4.3 DC Bus Regulation Loop (for PFC mode only)
      4. 2.4.4 Soft Start Around Zero Crossing for Eliminate or Reduce Current Spike
      5. 2.4.5 AC Drop Test
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Base Board Settings
        2. 3.1.1.2 Control Card Settings
      2. 3.1.2 Software
        1. 3.1.2.1 Opening Project Inside CCS
        2. 3.1.2.2 Project Structure
        3. 3.1.2.3 Using CLA on C2000 MCU to Alleviate CPU Burden
        4. 3.1.2.4 CPU and CLA Utilization and Memory Allocation
        5. 3.1.2.5 Running the Project
          1. 3.1.2.5.1 Lab 1: Open Loop, DC (PFC Mode)
            1. 3.1.2.5.1.1 Setting Software Options for LAB 1
            2. 3.1.2.5.1.2 Building and Loading Project
            3. 3.1.2.5.1.3 Setup Debug Environment Windows
            4. 3.1.2.5.1.4 Using Real-Time Emulation
            5. 3.1.2.5.1.5 Running Code
          2. 3.1.2.5.2 Lab 2: Closed Current Loop DC (PFC)
            1. 3.1.2.5.2.1 Setting Software Options for Lab 2
            2. 3.1.2.5.2.2 Designing Current Loop Compensator
            3. 3.1.2.5.2.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.2.4 Running Code
          3. 3.1.2.5.3 Lab 3: Closed Current Loop, AC (PFC)
            1. 3.1.2.5.3.1 Setting Software Options for Lab 3
            2. 3.1.2.5.3.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.3.3 Running Code
          4. 3.1.2.5.4 Lab 4: Closed Voltage and Current Loop (PFC)
            1. 3.1.2.5.4.1 Setting Software Options for Lab 4
            2. 3.1.2.5.4.2 Designing Voltage Loop Compensator
            3. 3.1.2.5.4.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.4.4 Running Code
          5. 3.1.2.5.5 Lab 5: Open loop, DC (Inverter)
            1. 3.1.2.5.5.1 Setting Software Options for Lab 5
            2. 3.1.2.5.5.2 Building and Loading Project
            3. 3.1.2.5.5.3 Setup Debug Environment Windows
            4. 3.1.2.5.5.4 Running Code
          6. 3.1.2.5.6 Lab 6: Open loop, AC (Inverter)
            1. 3.1.2.5.6.1 Setting Software Options for Lab 6
            2. 3.1.2.5.6.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.6.3 Running Code
          7. 3.1.2.5.7 Lab 7: Closed Current Loop, DC (Inverter with resistive load)
            1. 3.1.2.5.7.1 Setting Software Options for Lab 7
            2. 3.1.2.5.7.2 Designing Current Loop Compensator
            3. 3.1.2.5.7.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.7.4 Running Code
          8. 3.1.2.5.8 Lab 8: Closed Current Loop, AC (Inverter with resistive load)
            1. 3.1.2.5.8.1 Setting Software Options for Lab 8
            2. 3.1.2.5.8.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.8.3 Running Code
          9. 3.1.2.5.9 Lab 9: Closed Current Loop (Grid Connected Inverter)
            1. 3.1.2.5.9.1 Setting Software Options for Lab 9
            2. 3.1.2.5.9.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.9.3 Running Code: Emulated Grid-tied Condition (Verification purpose only)
            4. 3.1.2.5.9.4 Running Code: Grid-tied Condition
        6. 3.1.2.6 Running Code on CLA
        7. 3.1.2.7 Advanced Options
          1. 3.1.2.7.1 Input Cap Compensation for PF Improvement Under Light Load
          2. 3.1.2.7.2 83
          3. 3.1.2.7.3 Adaptive Dead Time for Efficiency Improvements
          4. 3.1.2.7.4 Phase Shedding for Efficiency Improvements
          5. 3.1.2.7.5 Non-Linear Voltage Loop for Transient Reduction
          6. 3.1.2.7.6 Software Phase Locked Loop Methods: SOGI - FLL
    2. 3.2 Testing and Results
      1. 3.2.1 Test Results at Input 120 Vrms, 60 Hz, Output 380-V DC
        1. 3.2.1.1 Startup
        2. 3.2.1.2 Steady State Condition
        3. 3.2.1.3 Transient Test With Step Load Change
          1. 3.2.1.3.1 0% to 50% Load Step Change
          2. 3.2.1.3.2 50% to 100% Load Step Change
          3. 3.2.1.3.3 100% to 50% Load Step Change
          4. 3.2.1.3.4 50% to 100% Load Step Change
      2. 3.2.2 Test Results at Input 230 Vrms, 50 Hz, Output 380 V DC
        1. 3.2.2.1 Startup
        2. 3.2.2.2 Steady State Condition
        3. 3.2.2.3 Transient Test With Step Load Change
          1. 3.2.2.3.1 33% to 100% Load Step Change
          2. 3.2.2.3.2 100% to 33% Load Step Change
      3. 3.2.3 Test Results Graphs
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7About the Author
  13. 8Revision History
3.1.2.5.2.4 Running Code
  1. The project is programmed to drive the inrush relay and clear the trip after a set amount of time, that is, autoStartSlew==100. The software is programmed to do so in this lab. An input voltage must be applied after hitting run and before this autoslew counter reaches 100. If the counter reaches 100, before voltage is applied at the input, the code must be reset. For which the controller must be brought out of real time mode, a reset performed and restarted. Repeat steps from 3
  2. Now run the project by clicking GUID-0E577519-64C9-4C89-A28C-975CCF35D80F-low.png.
  3. Apply an input voltage of approximately 50 V before the TTPLPFC_autoStartSlew reaches 100. As soon TTPLPFC_autoStartSlew reaches 100, the inrush relay is triggered, and PWM trip is cleared along with closing the current loop flag.
    GUID-B4EC4367-1AA8-48C4-8EBE-4606FDA55723-low.pngFigure 3-16 Watch Expression, Lab 2, After Closed Current Loop Operation Begins
  4. The input current regulates around 0.7 A, and the output voltage boosts to approximately 128 V.
  5. Now slowly increase TTPLPFC_ac_cur_ref_pu to 0.1, that is, 2.5-A input.
  6. Next slowly increase Vin = 120 V, and the output voltage will be greater than 350 V.
    GUID-610AF87D-76E3-43E0-8876-4498F8C7ED5D-low.pngFigure 3-17 Watch Expression, Lab 2, After Closed Current Loop Operation Begins at Full Voltage
  7. SFRA is integrated in the software of this build to verify the designed compensator provides enough gain and phase margin by measuring on hardware. To run the SFRA keep the project running, and from the cfg page, click on the SFRA icon. SFRA GUI appears.
  8. Select the options for the device on the SFRA GUI. For example, for F28004x select floating point. Click on Setup Connection. On the pop-up window uncheck the boot on connect option, and select an appropriate COM port. Ensure Boot on Connect is deselected. Click OK. Return to the SFRA GUI, and click Connect.
  9. The SFRA GUI connects to the device. A SFRA sweep can now be started by clicking Start Sweep. The complete SFRA sweep takes a few minutes to finish. Activity can be monitored by seeing the progress bar on the SFRA GUI and also checking the flashing of blue LED on the back on the control card that indicates UART activity. Once complete, a graph with the open loop plot appears. Comparing this with the measured plots, there is good correlation between the modeled and measured as shown in Figure 3-18. This verifies that the designed compensator is indeed stable and the model accurate. Note: the deviation at low frequency, less than 200 Hz, is expected and is a known phenomena, also the measurement shown here was taken with a DC source, if an AC source is used to emulate a DC source the output impedance of the AC source can result in deviations from the graph plotted below
    GUID-C47D03BE-4F62-4525-B9F4-04C0F7248FAE-low.gifFigure 3-18 SFRA Run vs Modeled Closed Current Loop, Open Loop Gain

    The frequency response data is also saved in the project folder under an SFRA data folder and is time stamped with the time of the SFRA run.

  10. Optionally one can use the measured frequency response of the plant to design the current compensator by clicking on the Compensation Designer again from the syscfg page and choose SFRA Data for plant option on the GUI. This uses the measured plant information to design the compensator. This option can be used to fine tune the compensation. By default the compensation designer points to the latest SFRA run. If a previous SFRA run plant information must be used the user can select the SFRAData.csv file by browsing to it by clicking on Browse SFRA Data.
  11. This action verifies the current compensator design.
  12. To bring the system to a safe stop, bring the input DC voltage down to zero, observe the TTPLPFC_vBus_sensed_Volts comes down to zero as well.
  13. Fully halting the MCU when in real-time mode is a two-step process. First halt the processor by using the Halt button on the toolbar (GUID-CEC61420-51B7-45ED-A276-0E2E645982AD-low.png) or by using Target → Halt. Then take the MCU out of real-time mode by clicking on GUID-F443C7B8-178A-4910-9044-9BC0FA9477F3-low.png. Finally, reset the MCU (GUID-8E8358D6-E5B2-4960-9A30-90C9B77C035B-low.png) .
  14. Close the CCS debug session by clicking Terminate Debug Session (Target → Terminate all).
    GUID-38039C67-CB5D-4301-8BC2-3B268FD4BD48-low.png