TIDUFB6 December   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Multiplexer Network and Switch Strategy
      2. 2.2.2 Cell Balancing
      3. 2.2.3 Stacked AFE Communication
      4. 2.2.4 MCU and CAN Interface
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ78706
      2. 2.3.2 TMUX1308
      3. 2.3.3 TCAN1044-Q1
      4. 2.3.4 MSPM0G3519
      5. 2.3.5 LMR51406
      6. 2.3.6 ISO7731
      7. 2.3.7 UCC33420
      8. 2.3.8 UCC33421
      9. 2.3.9 TMP61
  9. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Daisy Chain
      2. 3.3.2 Cell Voltage Accuracy
      3. 3.3.3 Temperature Sensing Using TMP61
      4. 3.3.4 Temperature Sensing Timings
      5. 3.3.5 Cell Balancing and Thermal Performance
      6. 3.3.6 Current Consumption
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.3.4 MSPM0G3519

MSPM0Gx51x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU family based on the enhanced Arm Cortex-M0+ 32-bit core platform, operating at up to 80MHz frequency. These MCUs offer a blend of cost optimization and design flexibility for applications requiring 256KB to 512KB of flash memory in small packages (down to 5mm × 5mm) or high pin count packages (up to 100 pins). These devices include dual CAN-FD controllers, cybersecurity enablers, high-performance integrated analog, and provide excellent low-power performance across the operating temperature range.

Up to 512KB of embedded flash program memory with built-in error correction code (ECC) and up to 128KB SRAM (with ECC and parity protection for the first 64KB). The flash memory is organized into two main banks to support field firmware updates, with address swap support provided between the two main banks.

Flexible cybersecurity enablers can be used to support secure boot, secure in-field firmware updates, IP protection (execute-only memory), key storage, and more. Hardware acceleration is provided for a variety of AES symmetric cipher modes, as well as a TRNG entropy source. The cybersecurity architecture is pending Arm® PSA Level 1 certification.

A set of high-performance analog modules is provided, such as two simultaneously sampling 12-bit 4Msps ADCs supporting up to 27 external channels, on-chip voltage reference (1.4V or 2.5V), one 12-bit 1Msps DAC, and three high-speed comparators with built-in 8-bit reference DACs operable in low-power and high-speed modes.

The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers to find the MCU that meets the needs of the project. The MSPM0 MCU platform combines the Arm® Cortex®-M0+ platform with a holistic ultra-low-power system architecture, allowing system designers to increase performance while reducing energy consumption.