TIDUFC1 November 2025
Figure 4-10 shows the TINA-TI schematic used to simulate the complete signal chain noise. Figure 4-11 shows the simulation results. DMM noise is often specified in numbers of power line cycles (PLC), which represents one cycle of the power line frequency. A higher PLC indicates a longer measurement integration time. For example, 5 PLC indicates the DMM measured for 5 power line cycles. A higher PLC results in a more accurate measurement at the cost of increased measurement time. At 60Hz, or 1 PLC, the simulated noise is less than 1μVRMS.
Figure 4-10 TIDA-010970 TINA-TI Simulation Schematic
Figure 4-11 Total Noise for TIDA-010970 for All Input Ranges