TIDUFC1 November 2025
This design uses REF81, a highly stable buried-Zener reference for calibrating the signal chain. A precision resistor divider network (RES11A) generates additional calibration source signals for the 1V and 100mV input ranges, as shown in Figure 3-3. An input multiplexer (MUX36) selects between the input signal, the calibration source signals for each input range, and ground.
The 10V range calibration source originates directly from REF81, making this range the most accurate calibration range available. The calibration sources for the 1V and 100mV ranges are slightly less accurate since those sources are derived from the 10V signal. Any error from the precision resistor divider used to generate the 1V and 100mV sources is present. This reference design uses a near full-scale signal to maximize the calibrated error across the entire input range.
The calibration source calibrates the entire signal chain. Repeated calibration between measurements continuously removes initial gain and offset error from every measurement. This continuous calibration removes offset and gain error drift as well. Therefore, the only remaining errors in the system are the noise and linearity of the signal chain, as well as the drift of the calibration source. The calibration source must be stable over time and temperature to reduce errors from long-term and temperature drift because the overall signal chain accuracy depends on the calibration source. Nonlinearity and noise become the dominant sources of error with a stable calibration source. Reduce these error sources with careful component selection, as discussed in Section 3.2.
Use the following procedure to implement a continuous calibration routine. Software can implement this routine automatically, and one full cycle of the calibration routine is required to produce an accurate measurement. Figure 3-4 shows this process.
Apply the gain and offset values to the ADS127L21B GAIN and OFFSET registers so ADS127L21B automatically applies gain and offset corrections to the conversion data. The value in the OFFSET registers is first subtracted from the conversion result. Next, the value in the GAIN registers is multiplied by the conversion result divided by 400000h. See the Calibration section of the ADS127L21B 512kSPS, High-Precision, 24-Bit, Wideband Delta-Sigma ADC datasheet for more details.
This calibration routine measures the input twice during one cycle. Measuring the input twice allows the DMM to measure the input at half the sampling rate, rather than one-third the sampling rate since the DMM measures the input at every other measurement. For example, a DMM executing the calibration routine at 60SPS has an effective measurement rate of 30SPS. Alternatively, operate the DMM at 120SPS to take a 60SPS measurement. Additionally, a continuous routine calibration requires a multiplexer with fast settling time to take accurate measurements.