TIDUFC1 November   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L21B
      2. 2.3.2 REF81
      3. 2.3.3 REF54
      4. 2.3.4 RES21A
      5. 2.3.5 THP210
      6. 2.3.6 OPA828
  9. 3System Design Theory
    1. 3.1 Range Selection
    2. 3.2 Linearity and Low-Noise Signal Chain
    3. 3.3 Calibration
    4. 3.4 Additional System Design Considerations
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 PCB Interface
      2. 4.1.2 Input Multiplexer
      3. 4.1.3 Gain Multiplexer
      4. 4.1.4 Power Supplies
      5. 4.1.5 Clock Tree
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Integral Nonlinearity Measurements
      2. 4.4.2 Noise Simulation
      3. 4.4.3 Noise Measurements
      4. 4.4.4 Conclusion
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

4.1.5 Clock Tree

This reference design supports three different clock options:

  1. PHI clock (no external connections)
  2. Local clock (no external connections)
  3. External clock

The default position for jumper JP4 is 2–3, which routes the PHI digital controller board clock to the CLK pin on the ADS127L21 (U10). Move the jumper to position 1–2 to directly route the local clock to ADS127L21 if the PCB is used without the PHI controller. Position 2–3 on jumper JP5 enables the local 32.768MHz oscillator (Y1) on the PCB, which is the default position required to work with the ADS127L21EVM-PDK-GUI software (see the ADS127L21EVM-PDK tool page). Supply an external clock with jumper J5 in position 1–2. Use a CMOS square-wave signal with an amplitude equal to IOVDD (2.5V when using the PHI board) and a frequency within the specified ADS127L21B range.

TIDA-010970 Clock Tree SchematicFigure 4-6 Clock Tree Schematic