TIDUFC3 January   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Power Topology
      2. 2.2.2 PCB and Form Factor
      3. 2.2.3 Antenna
    3. 2.3 Highlighted Products
      1. 2.3.1 AWRL6432BGAMFQ1
      2. 2.3.2 TCAN3404DDFRQ1
      3. 2.3.3 TPS65036x-Q1
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Getting Started With Hardware
        1. 3.1.1.1 Power Up Option
      2. 3.1.2 Sense-on-Power (SOP)
      3. 3.1.3 AWRL6432 Initialization: Board Programming
    2. 3.2 Test Setup
    3. 3.3 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints
      4. 4.1.4 Altium Project
      5. 4.1.5 Gerber Files
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

3.1.1.1 Power Up Option

Figure 3-1 shows the connections for power up.

TIDEP-01037 Connections for Power Up Figure 3-1 Connections for Power Up

Use the following steps for powering up the reference design for the power-up option:

  1. Connect the VBAT (J2.2 or J3.2) pin to a 12V DC supply. In Figure 3-1, VBAT is supplied to J2.2.
  2. Connect the GND pin of the DC supply to the GND pin of the reference design or to the GND pin of LP-XDS110 to provide the common GND across the setup
  3. Put a jumper on the 2-3 pin of the LP-XDS110 P9 connector to make sure the 3.3V IO supply is provided by the reference design to the LP-XDS110
  4. Connect the J1 connector with the bottom 10 pins of the LP-XDS110 using a female-to-female connector. See Figure 3-1.
  5. Power up the LP-XDS110 using a USB Type-C® cable
  6. Make sure the Sense-on-Power (SOP) lines are in correct configuration while powering up the device. See Section 3.1.2 for proper SOP configurations.
  7. nRESET can be issued through the LP-XDS110 reset switch since the J1.6 pin connects to the LP-XDS110 nRST pin

Alternatively, VBAT can also be provided from J1.2 after populating the R10 resistor.