74ACT11074

ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

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Product details

Parameters

Channels (#) 2 Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 100 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns), Positive input clamp diode open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 open-in-new Find other D-type flip-flop

Features

  • Inputs Are TTL-Voltage Compatible
  • Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)

 

EPIC is a trademark of Texas Instruments Incorporated.

open-in-new Find other D-type flip-flop

Description

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from -40°C to 85°C.

open-in-new Find other D-type flip-flop
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Dual D-Type Positive-Edge-Triggered Flip Flop With Clear And Preset datasheet (Rev. A) Apr. 01, 1996
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options

Ordering & quality

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