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High-speed ADCs (≥10 MSPS)

ADC12DJ4000RF

ACTIVE

RF-sampling 12-bit ADC with 4-GSPS dual channel or 8-GSPS single channel

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Data sheet

ADC12DJ4000RF

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 4000, 8000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3650 Architecture Folding Interpolating SNR (dB) 57 ENOB (Bits) 9 SFDR (dB) 66 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 4000, 8000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3650 Architecture Folding Interpolating SNR (dB) 57 ENOB (Bits) 9 SFDR (dB) 66 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10 FCCSP (ZEG) 144 100 mm² 10 x 10
  • ADC core:
    • 12-bit resolution
    • Up to 8GSPS in single-channel mode
    • Up to 4GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1VPP-DIFF):
      • Dual-channel mode: –152.3dBFS/Hz
      • Single-channel mode: –155dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz): 8.8 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3dB): 8GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.7W
  • Power supplies: 1.1V, 1.9V
  • ADC core:
    • 12-bit resolution
    • Up to 8GSPS in single-channel mode
    • Up to 4GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1VPP-DIFF):
      • Dual-channel mode: –152.3dBFS/Hz
      • Single-channel mode: –155dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz): 8.8 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3dB): 8GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.7W
  • Power supplies: 1.1V, 1.9V

The ADC12DJ4000RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ4000RF can be configured as a dual-channel, 4 GSPS ADC or single-channel, 8 GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ4000RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

The ADC12DJ4000RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ4000RF can be configured as a dual-channel, 4 GSPS ADC or single-channel, 8 GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ4000RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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Technical documentation

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* Data sheet ADC12DJ4000RF 8GSPS Single-Channel or 4GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. D) PDF | HTML 08 Apr 2025
Application note Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 28 Mar 2025
Application note Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 26 Mar 2025
Technical article So, what are S-parameters anyway? PDF | HTML 23 May 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12DJ4000RFEVM — ADC12DJ4000RF evaluation module for 4GSPS dual- or 8GSPS single-channel, RF-sampling, 12-bit ADC

The ADC12DJ4000RF evaluation module (EVM) is designed to evaluate the ADC12DJ4000RF high-speed analog-to-digital converter (ADCs). The EVM is populated with the ADC12DJ4000RF, a 12-bit, dual-channel 4GSPS or single-channel 8GSPS ADC with JESD204B interface.
User guide: PDF | HTML
Not available on TI.com
Evaluation board

TRF1208-ADC12DJ5200RFEVM — TRF1208 evaluation module for high-speed RF-sampling fully-differential amplifier with ADC12DJ5200RF

The TRF1208-ADC12DJ5200RF evaluation module (EVM) is designed to evaluate the ADC12DJ5200RF family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ5200RF, a 12-bit, dual-channel 5.2GSPS or single-channel 10.4GSPS ADC with JESD204B interface and allows for (...)
User guide: PDF | HTML
Not available on TI.com
Firmware

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

Supported products & hardware

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Calculation tool

ADC12DJ5200RF-CALC — ADC12DJ5200RF input network full-scale calculation tool.

Calculation tool referenced in application note SLVAFZ7.
Supported products & hardware

Supported products & hardware
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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FCCSP (AAV) 144 Ultra Librarian
FCCSP (ZEG) 144 Ultra Librarian
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