The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | ADC08DJ5200RF 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. B) | PDF | HTML | 08 Apr 2025 |
| Application note | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 28 Mar 2025 | |
| Application note | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 26 Mar 2025 |
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The ADC08DJ5200RF evaluation module (EVM) is a platform for evaluating the ADC08DJ5200RF. ADC08DJ5200RF is a low-power, 8-bit, dual-channel 5.2-GSPS or single-channel 10.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input and integrated digital downconverter, which (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
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Initial Release