CMOS 14-Stage Ripple-Carry Binary Counter/Divider and Oscillator
Product details
Parameters
Package | Pins | Size
Features
- 12 MHz clock rate at 15 V
- Common reset
- Fully static operation
- Buffered inputs and outputs
- Schmitt trigger input-pulse line
- 100% tested for quiescent current at 20 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices’
- Oscillator Features:
- All active components on chip
- RC or crystal oscillator configuration
- RC oscillator frequency of 690 kHz min. at 15 V
- Applications
- Control counters
- Timers
- Frequency dividers
- Time-delay circuits
Description
CD4060B consists of an oscillator section and 14 ripple-carry binary counter stages.
The oscillator configuration allows design of either RC or crystal oscillator circuits.
A RESET input is provided which resets the counter to the all-O's state and disables the oscillator.
A high level on the RESET line accomplishes the reset function. All counter stages are master-slave flip-flops.
The state of the counter is advanced one step in binary order on the negative transition of
O).
All inputs and outputs are fully buffered. Schmitt trigger action on the input-pulse line permits unlimited input-pulse
rise and fall times.
The CD4060B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | CD4060B Types datasheet (Rev. C) | Oct. 14, 2003 |
Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
User guide | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
User guide | Signal Switch Data Book (Rev. A) | Nov. 14, 2003 | |
More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | Dec. 03, 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
PDIP (N) | 16 | View options |
SO (NS) | 16 | View options |
SOIC (D) | 16 | View options |
TSSOP (PW) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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