CD74ACT112 Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset | TI.com

CD74ACT112
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Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset

Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset - CD74ACT112
Datasheet
 

Description

The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

Features

  • Inputs Are TTL-Voltage Compatible
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Bits (#) Voltage (Nom) (V) F @ nom voltage (Max) (MHz) ICC @ nom voltage (Max) (mA) tpd @ nom Voltage (Max) (ns) IOL (Max) (mA) IOH (Max) (mA) Rating
CD74ACT112 Order now ACT     4.5     5.5     2     5     90     0.04     11.1     24     -24     Catalog    
CD54ACT112 Samples not available ACT     4.5     5.5     2     5     90     0.04     11.1     -24     24     Military