CD74ACT74-Q1

ACTIVE

Product details

Number of channels (#) 2 Technology Family ACT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 85 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 80 Features Balanced outputs, Very high speed (tpd 5-10ns), Positive input clamp diode
Number of channels (#) 2 Technology Family ACT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 85 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 80 Features Balanced outputs, Very high speed (tpd 5-10ns), Positive input clamp diode
SOIC (D) 14 52 mm² 8.65 x 6
  • Qualified for Automotive Applications
  • Inputs Are TTL-Voltage Compatible
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design

  • Qualified for Automotive Applications
  • Inputs Are TTL-Voltage Compatible
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design

The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

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Technical documentation

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Type Title Date
* Data sheet Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. A) 29 Jan 2008
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature Automotive Logic Devices Brochure 27 Aug 2014
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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SOIC (D) 14 View options

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